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분할-커패시터 기반의 차동 디지털-아날로그 변환기를 가진 10-bit 10-MS/s 0.18-㎛ CMOS 비동기 축차근사형 아날로그-디지털 변환기
정연호,장영찬,Jeong, Yeon-Ho,Jang, Young-Chan 한국정보통신학회 2013 한국정보통신학회논문지 Vol.17 No.2
본 논문은 분할-커패시터 기반의 차동 디지털-아날로그 변환기 (DAC: digital-to-analog converter)를 이용하는 10-bit 10-MS/s 비동기 축차근사형 (SAR: successive approximation register) 아날로그-디지털 변환기 (ADC: analog-to-digital converter)를 제안한다. 샘플링 주파수를 증가시키기 위해 SAR 로직과 비교기는 비동기로 동작을 한다. 또한 높은 해상도를 구현하기 위해 오프셋 보정기법이 적용된 시간-도메인 비교기를 사용한다. 제안하는 10-bit 10-MS/s 비동기 축차근사형 아날로그-디지털 변환기는 0.18-${\mu}m$ CMOS 공정에서 제작되며 면적은 $140{\times}420{\mu}m^2$이다. 1.8 V의 공급전압에서 전력소모는 1.19 mW이다. 101 kHz 아날로그 입력신호에 대해 측정된 SNDR은 49.95 dB이며, DNL과 INL은 각각 +0.57/-0.67, +1.73/-1.58이다. This paper describes a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) using a split-capacitor-based differential digital-to-analog converter (DAC). SAR logic and comparator are asynchronously operated to increase the sampling frequency. The time-domain comparator with an offset calibration technique is used to achieve a high resolution. The proposed 10-bit 10-MS/s asynchronous SAR ADC with the area of $140{\times}420{\mu}m^2$ is fabricated using a 0.18-${\mu}m$ CMOS process. Its power consumption is 1.19 mW at 1.8 V supply. The measured SNDR is 49.95 dB for the analog input frequency of 101 kHz. The DNL and INL are +0.57/-0.67 and +1.73/-1.58, respectively.
MOM 커패시터를 사용한 디지털-아날로그 변환기를 가진 10-bit 10-MS/s 비동기 축차근사형 아날로그-디지털 변환기
정연호,장영찬,Jeong, Yeon-Ho,Jang, Young-Chan 한국정보통신학회 2014 한국정보통신학회논문지 Vol.18 No.1
본 논문은 디지털-아날로그 변환기(DAC: digital-to-analog converter), SAR 로직, 그리고 비교기로 구성된 10-bit 10-MS/s 비동기 축차근사형(SAR: successive approximation register) 아날로그-디지털 변환기(ADC: analog-to-digital converter)를 제안한다. Rail-to-rail의 입력 범위를 가지는 설계된 비동기 축차근사형 아날로그-디지털 변환기는 샘플링 속도를 향상시키기 위해 MOM(metal-oxide-metal) 커패시터를 이용한 바이너리 가중치 기반의 디지털-아날로그 변환기를 사용하여 구현한다. 제안하는 10-bit 10-MS/s 비동기 축차근사형 아날로그-디지털 변환기는 0.18-${\mu}m$ CMOS 공정에서 제작되고 면적은 $0.103mm^2$를 차지한다. 1.1 V의 공급전압에서 전력소모는 0.37 mW를 나타낸다. 101.12 kHz와 5.12 MHz의 아날로그 입력 신호에 대해 측정된 SNDR은 각각 54.19 dB와 51.59 dB이다. This paper presents a 10-bit 10-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) which consists of a digital-to-analog converter (DAC), a SAR logic, and a comparator. The designed asynchronous SAR ADC with a rail-to-rail input range uses a binary weighted DAC using metal-oxide-metal (MOM) capacitor to improve sampling rate. The proposed 10-bit 10-MS/s asynchronous SAR ADC is fabricated using a 0.18-${\mu}m$ CMOS process and its active area is $0.103mm^2$. The power consumption is 0.37 mW when the voltage of supply is 1.1 V. The measured SNDR are 54.19 dB and 51.59 dB at the analog input frequency of 101.12 kHz and 5.12 MHz, respectively.
정연호(Jeong Yeon-ho),김영범(Kim Young-bum),정호열(Jeong ho-youl),심영권(Shim young-kwon),최승욱(Choi seung-wook),문재휘(Moon Jae-Hui) 대한기계학회 2014 대한기계학회 춘추학술대회 Vol.2014 No.11
Steam soot-blower control valves for thermal power plants operate in a uniquely severe service and environment. They must not only frequently modulate flow over a wide range but must also maintain downstream pressure between very close limits at high differential. In addition, they also must function as block valves with tight shutoff every time they close to prevent soot-blower header pressure safety relief valve operation due to system overpressure. Satisfactory operation in these two separate functions is a problem often found in the power industry. Because of poor valve operating experience the soot-blower control valves were recently replaced with valves specifically designed for soot-blower service.
원전 2차계통 배관손상 실증시험설비(FAC) 설계 개발
정연호(Yeon-ho Jeong),김영범(Young-Bum Kim),김형근(Hyoung-Gun Kim),장훈(Hoon Jang),김홍표(Hong-Pyo Kim),김경모(Kyoung-Mo Kim) 대한기계학회 2012 대한기계학회 춘추학술대회 Vol.2012 No.11
Flow Accelerated Corrosion (FAC) is a corrosion mechanism induced by a combination of various chemical, physical and hydrodynamic factors. Eventually, Under specific conditions, the oxide layer that protects the metal underneath becomes very thin. Among the different corrosion mechanisms that are encountered in power plants, a phenomenon known as FAC has been the subject of extensive experimental and theoretical studies. Test facility was designed to demonstrate FAC of secondary system of PWR. FAC test facility is expected to improve the accuracy of the existing piping corrosion prediction program.
鄭然鎬(Yeon-Ho Jeong),崔永旭(Young-Wook Choi) 대한전기학회 2007 전기학회논문지 Vol.56 No.12
In this paper, to produce sheet plasma with high density for ion plating, we designed magnetic circuit of ion plating device consisting of solenoid coil and rectangular permanent magnet. And, we analyzed the effects of the magnetic field distribution using FEM (Finite Element Methode). Additionally, we made a sputtering system including ion plating technique on the basis of the design and verified the possibility of the sheet plasma application for advanced sputter system.