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공익사업을 위한 토지 등의 취득과 그 손실보상에 있어 행정형 대체적 분쟁해결제도 연구
정기상 ( Ki Sang Jung ) 한양대학교 법학연구소 2012 법학논총 Vol.29 No.4
『Act on the Acquisition of Land etc. for Public Works and the Compensation』stipulates the confirmation of reaching agreements and the recommendation of compromise by the land commission as ‘administrative’ alternative dispute resolutions in the acquisition of land etc. for public works and the compensation. But the confirmation of reaching agreements and the recommendation of compromise are not widely used on account of ambiguous provisions related to each resolution. If the business operator, landowners and the parties concerned accept the recommendation of compromise, the land commission makes the compromise protocol. Ambiguous provisions related to the legal effects of the compromise protocol arouse the controversy about the practical benefit of the recommendation of compromise. It is necessary to amend the provisions related to the confirmation of reaching agreements and the recommendation of compromise to make plain the procedures and the legal effects. Especially, I suggest to give landowners and the parties concerned the rights to request the confirmation of reaching agreements. I don`t think there is any substantial reason to invest only business operators with the rights to request the confirmation. It is reasonable to let the land commission itself(not a subcommittee) recommend compromise to the business operator, landowners and the parties concerned. And the confirmation of reaching agreements and the recommendation of compromise are used after the notification of the public utility authorization. It is necessary to adopt administrative alternative dispute resolutions before the notification of the public utility authorization, such as arbitration and conciliation. Through this research, I hope the discussions on the related issues would be more active.
鄭基相(Ki-Sang Jung),金容恩(Yong-En Kim),趙成翊(Seong-Ik Cho) 대한전기학회 2007 전기학회논문지 Vol.56 No.11
In a memory, most power is dissipated in line of high capacitance such as decoder lines, word lines, and bit * lines. The decoder size as well as the parastic capacitances of the bit-line are going to reduce, if ROM core size reduces. This paper proposes to reduce a mathod of power dissipation for reducing ROM core size. Design result of ROM used in FFT[2], proposed method lead to up to 40.6%, 42.12%, 37.82% reduction in area, power consumption and number of Tr. respectively compared with previous method.
1/4-rate 위상선택방식을 이용한 클록 데이터 복원회로
정기상(Ki-Sang Jung),김강직(Kang-Jik Kim),조성익(Seong-Ik Cho) 대한전자공학회 2009 電子工學會論文誌-SC (System and control) Vol.46 No.1
본 논문은 시스템의 클록을 이용하여 클록 및 데이터를 복원하는 회로를 설계하였다. 설계된 회로에는 시스템의 클록을 만들어주는 PLL부분과 클록을 받아 데이터를 복원하는 데이터 복원회로부분으로 구성되어 있다. 데이터 복원회로에서는 1/4-rate 위상검출기를 이용하여 데이터보다 시스템의 클록주파수를 낮추어 설계하여 PLL의 부담을 줄일 수 있었고 데이터 picking 방식으로 설계하여 적은 지터특성을 보였다. 설계된 클록 데이터 복원회로는 0.18㎛ 1P6M CMOS공정으로 설계되었고 칩 면적은 1x1㎟이다. This work is design of clock and data recovery circuit using system clock. This circuit is composed by PLL(Phase Locked Loop) to make system clock and data recovery circuit. The data recovery circuit using 1/4-rate phase picking Detector helps to reduce clock frequency. It is advantageous for high speed PLL. It can achieve a low jitter operation. The designed CDR(Clock and data recovery) has been designed in a standard 0.18㎛ 1P6M CMOS technology and an active area 1x1㎟.
2-step DPC를 이용한 이중루프 DLL기반의 광대역 클록 데이터 복원회로 설계
정기상(Ki-Sang Jung),김강직(Kang-Jik Kim),고귀한(Gui-han Ko),조성익(Seong-Ik Cho) 대한전기학회 2012 전기학회논문지 Vol.61 No.2
A recovered jitter of CDR(Clock and Data Recovery) Circuit based on Dual-loop DLL(Delay Locked Loop) for data recovery in high speed serial data communication is changed by depending on the input data and reference clock frequency. In this paper, 2-step DPC which has constant jitter performance for wide-range input frequency is proposed. The designed prototype 2-step CDR using proposed 2-step DPC has operation frequency between 200Mbps and 4Gbps. Average delay step of 2-step DPC is 10ps. Designed CDR circuit was tested with 0.18um CMOS process.
고속 직렬 디스플레이 인터페이스를 위한 1/4-rate 클록 데이터 복원회로 설계
정기상(Ki-Sang Jung),김강직(Kang-Jik Kim),조성익(Seong-Ik Cho) 대한전기학회 2011 전기학회논문지 Vol.60 No.2
4:10 deserializer is proposed to recover 1:10 serial data using 1/4-rate clock. And then, 1/4-rate CDR(Clock and Data Recovery) circuit was designed for SERDES of high-speed serial display interface. The reduction of clock frequency using 1/4-rate clocking helps relax the speed limitation when higher data transfer is demanded. This circuit is composed of 1/4-rate sampler, PEL(Phase Error Logic), Majority Voting, Digital Filter, DPC(Digital to Phase Converter) and 4:10 deserializer. The designed CDR has been designed in a standard 0.18㎛ 1P6M CMOS technology and the recovered data jitter is 14ps in simulation
고귀한(Gwi-Han Go),정기상(Ki-Sang Jung),김강직(Kang-Jik Kim),조성익(Seong-Ik Cho) 대한전기학회 2012 전기학회논문지 Vol.61 No.11
This paper is proposed all digital wide?range clock and data recovery circuit. The Proposed clock data recovery circuit is possible input data rate which is suggested is wide-range that extends from 100Mb/s to 3Gb/s and used an phase error detector which can use a way of over-sampling a data by using a 1/2-rate multi-phase clock and phase rotator which is regular size per 2π/16 and can make a phase rotation. So it could make the phase rotating in range of input data rate. Also all circuit is designed as a digital which has a specificity against a noise. This circuit is designed to 0.13㎛ CMOS process and verified simulation to spectre tool.
시리얼 데이터 통신을 위한 기준 클록이 없는 3.2Gb/s 클록 데이터 복원회로
김강직(Kang-Jik Kim),정기상(Ki-Sang Jung),조성익(Seong-Ik Cho) 대한전자공학회 2009 電子工學會論文誌-SC (System and control) Vol.46 No.2
본 논문은 별도 기준 클록 없이 고속 시리얼 데이터 통신을 위한 3.2Gb/s 클록 데이터 복원(CDR) 회로를 설명한다. CDR회로는 전체적으로 5부분으로 구성되며, 위상검출기(PD)와 주파수 검출기(FD), 다중 위상 전압 제어 발진기(VCO), 전하펌프(CP), 외부 루프필터(LF)로 구성되어 있다. CDR회로는 half-rate bang-bang 타입의 위상 검출기와 입력 pull-in 범위를 늘릴 수 있도록 half-rate 주파수 검출기를 적용하였다. VCO는 4단의 차동 지연단(delay cell)으로 구성되어 있으며 튜닝 범위와 선형성 향상을 위해 rail-to-rail 전류 바이어스단을 적용하였다. 각 지연단은 풀 스윙과 듀티의 부정합을 보상할 수 있는 출력버퍼를 갖고 있다. 구현한 CDR회로는 별도의 기준 클록 없이 넓은 pull-in 범위를 확보할 수 있으며 기준 클록 생성을 위한 부가적인 Phase-Locked Loop를 필요치 않기 때문에 칩의 면적과 전력소비를 효과적으로 줄일 수 있다. 본 CDR 회로는 0.18㎛ 1P6M CMOS 공정을 이용하여 제작하였고 루프 필터를 제외한 전체 칩 면적은 1x1㎟이다. 3.2Gb/s 입력 데이터 율에서 모의실험을 통한 복원된 클록의 pk-pk 지터는 26ps이며 1.8V 전원전압에서 전체 전력소모는 63㎽로 나타났다. 동일한 입력 데이터 율에서 테스트를 통한 pk-pk 지터 결과는 55ps였으며 신뢰할 수 있는 입력 데이터율 범위는 약 2.4Gb/s에서 3.4Gb/s로 나타났다. In this paper, a 3.2Gb/s clock and data recovery (CDR) circuit for a high-speed serial data communication without the reference clock is described This CDR circuit consists of 5 parts as Phase and frequency detector(PD and FD), multi-phase Voltage Controlled-Oscillator(VCO), Charge-pumps(CP) and external Loop-Filter(LF). It is adopted the PD and FD, which incorporates a half-rate bang-bang type oversampling PD and a half-rate FD that can improve pull-in range. The VCO consists of four fully differential delay cells with rail-to-rail current bias scheme that can increase the tuning range and tuning linearity. Each delay cell has output buffers as a full-swing generator and a duty-cycle mismatch compensation. This materialized CDR can achieve wide pull-in range without an extra reference clock and it can be also reduced chip area and power consumption effectively because there is no additional Phase Locked- Loop(PLL) for generating reference clock. The CDR circuit was designed for fabrication using 0.18㎛ 1P6M CMOS process and total chip area excepted LF is 1x1㎟. The pk-pk jitter of recovered clock is 26ps at 3.2Gb/s input data rate and total power consumes 63㎽ from 1.8V supply voltage according to simulation results. According to test result, the pk-pk jitter of recovered clock is 55ps at the same input data-rate and the reliable range of input data-rate is about from 2.4Gb/s to 3.4Gb/s.
김강직(Kang-jik Kim),정기상(Ki-sang Jung),박원기(Won-ki Park),이성철(Sung-chul Lee),조성익(Seong-ik Cho) 대한전자공학회 2010 대한전자공학회 학술대회 Vol.2010 No.6
This paper is intended as design of a 3.4Gbps transmitter (TX) for multi-channel communication. It can be applied high-speed serial link system such as DVI, HDMI etc. This TX circuit can be classified into three main blocks: a PLL(Phase Locked Loop), a multiplexer stage as a data serializer and an output buffer stage for a driving of output data stream. In the output driver stage, pre-emphasis technique is applied to improve the effect of ISI. The fabricated HDMI TX PHY was designed using 0.18μm 1P5M CMOS technology. It was verified on maximum 3.4Gbps output data rate by measurement results and satisfied with HDMI 1.3a specification.