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Li, Yuhao,Liu, Rui,Yan, Zhangwei,Zhang, Xiangning,Zhu, Hongjun Korean Chemical Society 2010 Bulletin of the Korean Chemical Society Vol.31 No.11
A series of oxazolidinone-based strobilurin analogues were efficiently synthesized by the reaction of 3-(2-bromomethylphenyl) oxazolidin-2-one with 1-substituted phenyl-2H-pyrazolin-3-one. Their structures were confirmed and characterized by $^1H$-NMR, $^{13}C$-NMR, elemental analysis, and mass spectroscopy. In addition, the crystal structure of the target compound 3-(2-((1-phenyl-2H-pyrazol-3-yloxy)methyl)phenyl) oxazolidin-2-one was determined by single crystal X-ray diffraction. The bioassay results of these compounds indicated that some of the oxazolidin-2-one derivatives containing N-substituted phenyl 2H-pyrazol ring exhibited potential in vivo fungicidal activities against M. grisea at the dosage of $1\;g\;L^{-1}$.
Yuhao Li,Rui Liu,Zhangwei Yan,Xiangning Zhang,Hongjun Zhu 대한화학회 2010 Bulletin of the Korean Chemical Society Vol.31 No.11
A series of oxazolidinone-based strobilurin analogues were efficiently synthesized by the reaction of 3-(2-bromomethylphenyl)oxazolidin-2-one with 1-substituted phenyl-2H-pyrazolin-3-one. Their structures were confirmed and characterized by 1H-NMR, 13C-NMR, elemental analysis, and mass spectroscopy. In addition, the crystal structure of the target compound 3-(2-((1-phenyl-2H-pyrazol-3-yloxy)methyl)phenyl) oxazolidin-2-one was determined by single crystal X-ray diffraction. The bioassay results of these compounds indicated that some of the oxazolidin-2-one derivatives containing N-substituted phenyl 2H-pyrazol ring exhibited potential in vivo fungicidal activities against M. grisea at the dosage of 1 g L‒1.
Static Timing Analysis of Shared Caches for Multicore Processors
Zhang, Wei,Yan, Jun Korean Institute of Information Scientists and Eng 2012 Journal of Computing Science and Engineering Vol.6 No.4
The state-of-the-art techniques in multicore timing analysis are limited to analyze multicores with shared instruction caches only. This paper proposes a uniform framework to analyze the worst-case performance for both shared instruction caches and data caches in a multicore platform. Our approach is based on a new concept called address flow graph, which can be used to model both instruction and data accesses for timing analysis. Our experiments, as a proof-of-concept study, indicate that the proposed approach can accurately compute the worst-case performance for real-time threads running on a dual-core processor with a shared L2 cache (either to store instructions or data).