Clock Routing Synthesis for Nanometer IC Design

Jin, Xianzhe,Ryoo, Kwang-Ki The Korea Institute of Information and Commucation 2008 Journal of information and communication convergen Vol.6 No.4

Clock skew modeling is important in the performance evaluation and prediction of clock distribution network and it is one of the major constraints for high-speed operation of synchronous integrated circuits. In clock routing synthesis, it is necessary to reduce the clock skew under the specified skew bound, while minimizing the cost such as total wire length and delay. In this paper, a new efficient bounded clock skew routing method is described, which generalizes the well-known bounded skew tree method by allowing loops, i.e., link-edges can be inserted to a clock tree when they are beneficial to reduce the clock skew and/or the wire length. Furthermore, routing topology construction and wire sizing is used to reduce clock delay.

A Self-Adaptive Inter-Prediction Hardware Architecture Design for H.264/AVC Decoder

Xianzhe Jin,Kwangki Ryoo 한국정보통신학회 2009 2016 INTERNATIONAL CONFERENCE Vol.2 No.1

An Efficient Interpolation Hardware Architecture for HEVC Inter-Prediction Decoding

Jin, Xianzhe,Ryoo, Kwangki The Korea Institute of Information and Commucation 2013 Journal of information and communication convergen Vol.11 No.2

This paper proposes an efficient hardware architecture for high efficiency video coding (HEVC), which is the next generation video compression standard. It adopts several new coding techniques to reduce the bit rate by about 50% compared with the previous one. Unlike the previous H.264/AVC 6-tap interpolation filter, in HEVC, a one-dimensional seven-tap and eight-tap filter is adopted for luma interpolation, but it also increases the complexity and gate area in hardware implementation. In this paper, we propose a parallel architecture to boost the interpolation performance, achieving a luma $4{\times}4$ block interpolation in 2-4 cycles. The proposed architecture contains shared operations reducing the gate count increased due to the parallel architecture. This makes the area efficiency better than the previous design, in the best case, with the performance improved by about 75.15%. It is synthesized with the MagnaChip $0.18{\mu}m$ library and can reach the maximum frequency of 200 MHz.

A Performance-Oriented Intra-Prediction Hardware Design for H.264/AVC

Jin, Xianzhe,Ryoo, Kwangki The Korea Institute of Information and Commucation 2013 Journal of information and communication convergen Vol.11 No.1

In this paper, we propose a parallel intra-operation unit and a memory architecture for improving the performance of intra-prediction, which utilizes spatial correlation in an image to predict the blocks and contains 17 prediction modes in total. The design is targeted for portable devices applying H.264/AVC decoders. For boosting the performance of the proposed design, we adopt a parallel intra-operation unit that can achieve the prediction of 16 neighboring pixels at the same time. In the best case, it can achieve the computation of one luma $16{\times}16$ block within 16 cycles. For one luma $4{\times}4$ block, a mere one cycle is needed to finish the process of computation. Compared with the previous designs, the average cycle reduction rate is 78.01%, and the gate count is slightly reduced. The design is synthesized with the MagnaChip $0.18{mu}m$ library and can run at 125 MHz.

H.264/AVC 베이스라인 프로파일 디코더의 효율적인 인터예측 하드웨어 구조 설계

김선철(Jin, Xianzhe),류광기(Ryoo, Kwang-Ki) 한국산학기술학회 2009 한국산학기술학회논문지 Vol.10 No.12

본 논문에서는 H.264/AVC 베이스라인 프로파일 디코더 설계에서 병목현상을 일으키는 주요 부분인 인터 예 측 성능 개선을 위한 효율적인 하드웨어 구조를 제안한다. H.264/AVC 디코더는 다양한 블록 모드를 지원하지만 레퍼 런스 소프트웨어에서는 중복 픽셀에 대해 제거 하지 않고 항상 4x4 블록에 대하여 최소 4x4, 최대 9x9 참조 블록을 패치한다. 기존의 Nova에서는 이를 해결하기 위하여 8x8 블록 모드와 4x4 블록 모드를 고려하였다. 블록 모드가 8x8 사이즈보다 크거나 같을 경우 여러 8x8 블록으로 나누어서 그에 대한 13x13 레퍼런스 블록을 패치 하고 8x8 블록 보 다 작을 경우 여러 개의 4x4 블록으로 나누어 그에 대한 9x9 레퍼런스 블록을 패치하여 중복픽셀을 제거함으로써 사 이클 수를 감소시켜 레퍼런스 소프트웨어에 비해 최대 41.5%, 최소 28.2%의 성능을 향상시켰다. 본 논문에서는 성능 향상을 위하여 8x8과 4x4 블록 모드 뿐만 아니라 다양한 레퍼런스 블록 패치를 진행하여 중복픽셀을 제거하고 메모 리 패치 사이클 수를 줄여 기존 설계에 비해 최대 18.6%의 참조 블록 패치 사이클 수를 감소시켰다. Inter-prediction is always the main bottleneck in H.264/AVC baseline profile. This paper describes an efficient inter-prediction hardware architecture design. H.264/AVC decoder supports various block types but reference software considers only the 4x4 block when the reference block is being fetched. This causes duplicated pixels which needs extra fetch cycles. In order to eliminate some of the duplicated pixels, the 8x8 and 4x4 blocks were considered in the previous design. If the block size is larger than or equal to the 8x8 block, it will be decomposed into several 8x8 blocks and if the block size is smaller than the 8x8 block it will be decomposed into several 4x4 blocks. Comparing with the reference software, the maximum and minimum cycle reduction of the previous design are 41.5% and 28.2% respectively. For further reduction of the fetch cycles, the various block types are considered in this paper. As a result, the maximum cycle reduction is 18.6% comparing with the previous design.

H.264/AVC 복호기를 위한 고성능 연산처리 인트라 예측기 설계

김선철,류광기,Jin, Xianzhe,Ryoo, Kwangki 한국정보통신학회 2012 한국정보통신학회논문지 Vol.16 No.11

This paper proposes a parallel operation intra predictor for H.264/AVC decoder. In previous intra predictor design, common operation units were designed for 17 prediction modes in order to compute more effectively. However, it was designed by analyzing the equation applied to one pixel. So, there are four operation units for computing 16 pixels in a $4{\times}4$ block and they need four cycles. In this paper, the proposed intra predictor contains T3(Three Type Transform) operation unit for parallel operation. It divides 17 modes into 3 types to calculate 16 pixels of a $4{\times}4$ block in only one cycle and needs 16 cycles minimum in 16x16 block. As the result of the experiment, in terms of processing cycle, the performance of proposed intra predictor is 58.95% higher than the previous one. 본 논문에서는 H.264/AVC 복호기를 위한 고성능 연산처리 인트라 예측기를 제안한다. 기존의 인트라 예측기는 $4{\times}4$블록에 적용되는 17개의 예측모드를 효율적으로 연산하기 위해 공통 연산기를 사용하였다. 하지만 기존의 공통 연산기는 한 픽셀에 적용되는 연산 수식을 분석하여 설계되었기 때문에, 16개 픽셀의 $4{\times}4$ 블록을 연산하기 위해 4개의 공통 연산기를 사용하며 4 사이클을 소요한다. 본 논문에서는 병렬 연산을 위한 T3(Three Type Transform) 연산기를 제안한다. 제안하는 T3 연산기는 17개의 인트라 예측 모드를 3가지 형태로 나누어, $4{\times}4$ 블록의 16개 픽셀에 적용되는 연산 수식을 한 사이클에 처리한다. 제안하는 인트라 예측기와 기존의 인트라 예측기의 예측 수행 사이클을 각 모드 별로 비교한 결과, 제안하는 인트라 예측기가 평균 58.95%의 향상된 결과를 얻었다.

SoC Platform Design and Verification for Multimedia Application

Hongkyun Jung,Xianzhe Jin,Younjin Jung,Ok Kim,Byoungyup Lee,Kwangki Ryoo 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7

This paper proposes an SoC platform for the development of multimedia applications. The SoC platform uses a 32-bit RISC processor with 4-way set-associative cache for improvement of performance, a VGA controller and an AC97 controller for multimedia, an SoC debug interface for debugging and supports WISHBONE compatible peripheral IPs. The multimedia SoC platform is implemented on Xilinx VIRTEX-4 XC4VLX80 FPGA device and the FPGA executes at the maximum frequency of 64.574㎒. As a result of system-level verification using test programs in development board including the FPGA device, the proposed SoC platform was satisfactory for the desired functions.

Performance Improvement and Power Consumption Reduction of an Embedded RISC Core

Jung, Hong-Kyun,Jin, Xianzhe,Ryoo, Kwang-Ki The Korea Institute of Information and Commucation 2012 Journal of information and communication convergen Vol.10 No.1

This paper presents a branch prediction algorithm and a 4-way set-associative cache for performance improvement of an embedded RISC core and a clock-gating algorithm with observability don’t care (ODC) operation to reduce the power consumption of the core. The branch prediction algorithm has a structure using a branch target buffer (BTB) and 4-way set associative cache that has a lower miss rate than a direct-mapped cache. Pseudo-least recently used (LRU) policy is used for reducing the number of LRU bits. The clock-gating algorithm reduces dynamic power consumption. As a result of estimation of the performance and the dynamic power, the performance of the OpenRISC core applied to the proposed architecture is improved about 29% and the dynamic power of the core with the Chartered 0.18 ${\mu}m$ technology library is reduced by 16%.