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Yokoyama, Tomoki,Doi, Nobuaki,Ishioka, Toshiya The Korean Institute of Power Electronics 2009 JOURNAL OF POWER ELECTRONICS Vol.9 No.3
This paper proposes an autonomous decentralized control for a parallel connected uninterruptible power supply (UPS) system based on a fast power detection method using a FPGA based hardware controller for a single phase system. Each UPS unit detects only its output voltage and current without communications signal exchange and a quasi dq transformation method is applied to detect the phase and amplitude of the output voltage and the output current for the single phase system. Fast power detection can be achieved based on a quasi dq transformation, which results in a realization of very fast transient response under rapid load change. In the proposed method, the entire control system is implemented in one FPGA chip. Complicated calculations are assigned to hardware calculation logic, and the parallel processing circuit makes it possible to realize minimized calculation time. Also, an Nios II CPU core is implemented in the same FPGA chip, and the software can be applied for non-time critical calculations. Applying this control system, an autonomous decentralized UPS system with very fast transient response is realized. Feasibility and stable operation are confirmed by means of an experimental setup with three UPSs connected in parallel. Also, rapid load change is applied and excellent performance of the system is confirmed in terms of transient response and stability.
Tomoki Yokoyama,Nobuaki Doi,Toshiya Ishioka 전력전자학회 2009 JOURNAL OF POWER ELECTRONICS Vol.9 No.3
This paper proposes an autonomous decentralized control for a parallel connected uninterruptible power supply (UPS) system based on a fast power detection method using a FPGA based hardware controller for a single phase system. Each UPS unit detects only its output voltage and current without communications signal exchange and a quasi dq transformation method is applied to detect the phase and amplitude of the output voltage and the output current for the single phase system. Fast power detection can be achieved based on a quasi dq transformation, which results in a realization of very fast transient response under rapid load change. In the proposed method, the entire control system is implemented in one FPGA chip. Complicated calculations are assigned to hardware calculation logic, and the parallel processing circuit makes it possible to realize minimized calculation time. Also, an Nios II CPU core is implemented in the same FPGA chip, and the software can be applied for non-time critical calculations. Applying this control system, an autonomous decentralized UPS system with very fast transient response is realized. Feasibility and stable operation are confirmed by means of an experimental setup with three UPSs connected in parallel. Also, rapid load change is applied and excellent performance of the system is confirmed in terms of transient response and stability.
Experimental Verification of Weighted Moving Average 1MHz Multisampling Deadbeat Control for PMSM
Arata Takahash,Tomoki Yokoyama 전력전자학회 2019 ICPE(ISPE)논문집 Vol.2019 No.5
A new digital control method for permanent magnet synchronous motor based on deadbeat control with multisampling method using FPGA based hardware controller is proposed. Adopting FPGA based hardware controller, all the control calculation can be finished within around 800 nano second, which result in the realization of the ideal digital control feedback without any sampling compensation method, and superior transient characteristics can be obtained. In this paper, weighted moving average 1MHz multisampling deadbeat control was proposed and compared with the conventional deadbeat control method through simulations and experiments. The advantages of the proposed method was verified.
Verification of Autonomous Decentralized Control UPS system using FPGA based Hardware Controller
Tsuyoshi Saito,Nobuaki Doi,Tomoki Yokoyama 전력전자학회 2007 ICPE(ISPE)논문집 Vol.- No.-
Design concept of FPGA based hardware controller with HW/SW codesign for autonomous decentralized control UPS system is proposed. Progress of FPGA technology makes it possible to include the software macro CPU core into the FPGA chip, a high flexibility can be realized for the construction of the control processor in power electronics application. In the proposed method, all the control system is implemented in one FPGA chip. Complicated calculations are assigned to hardware calculation logic, and the parallel processing circuit makes it possible to realize minimizing the calculation time. Also Nios II CPU core is implemented in the same FPGA chip, and the software development can be applied for non-time critical calculations.The advantages of the proposed system is discussed through simulations and experiments.
( Taku Kobayashi ),( Hiroaki Ito ),( Toshifumi Ashida ),( Tadashi Yokoyama ),( Masakazu Nagahori ),( Tomoki Inaba ),( Mitsuhiro Shikamura ),( Takayoshi Yamaguchi ),( Tetsuharu Hori ),( Philippe Pinton 대한장연구학회 2021 Intestinal Research Vol.19 No.4
Background/Aims: A subgroup analysis was conducted in Japanese patients with moderate to severe ulcerative colitis (UC) enrolled in the phase 3 VISIBLE 1 study, which evaluated the safety and efficacy of a new vedolizumab subcutaneous (SC) for-mulation. Methods: Eligible patients received open-label infusions of vedolizumab 300 mg intravenous (IV) at weeks 0 and 2 in the induction phase. Patients with clinical response by complete Mayo score at week 6 entered the double-blind maintenance phase and were randomized to vedolizumab 108 mg SC every 2 weeks, placebo, or vedolizumab 300 mg IV every 8 weeks. The primary endpoint was clinical remission (complete Mayo score ≤2 points; no individual subscore >1 point) at week 52. Results: Of 49 patients who entered the induction phase, 22 out of 49 patients (45%) had clinical response at week 6 and were randomized to vedolizumab 108 mg SC (n=10), placebo (n=10), or vedolizumab 300 mg IV (n=2). At week 52, 4 out of 10 pa-tients (40%) who received vedolizumab SC had clinical remission versus 2 out of 10 patients (20%) who received placebo (dif-ference: 20% [95% confidence interval, ±27.9 to 61.8]). Two patients (2/10, 20%) who received vedolizumab SC experienced an injection-site reaction versus none who received placebo. Conclusions: Our results indicate that the efficacy of vedolizumab SC in a subgroup of Japanese patients with UC are similar with those in the overall VISIBLE 1 study population, and with those established with vedolizumab IV. The safety and tolerability of vedolizumab SC were generally similar to that established for vedolizumab IV. (ClinicalTrials.gov ID NCT02611830; EudraCT 2015-000480-14) (Intest Res 2021;19:448-460)
Yusuke Tajima,Yuta Hori,Takayuki Ino,Tomoki Yokoyama,Lazhar Ben-Brahim,Mohamed Trabelsi 전력전자학회 2011 ICPE(ISPE)논문집 Vol.2011 No.5
Multi-cell inverter include an array of single-phase inverters capable of handling higher voltage ratings with lower rating power electronics devices. In this paper, a deadbeat control combined with a multi-sampling compensation method is proposed to control a Variable Frequency Drive (VFD) fed by a multi-cell inverter and realize real time digital feedback control using FPGA based hardware controller. This digital control is characterized by a very fast transient response, low switching losses, and a proper compensation for load disturbances and cyclical fluctuations.
1MHz Variable Sampling Deadbeat Control for PM motor using FPGA
Asahi Kitada,Kota Miyata,Kota Tsuchiya,Hiroki Sato,Tomoki Yokoyama 전력전자학회 2015 ICPE(ISPE)논문집 Vol.2015 No.6
A new digital control method for permanent magnet synchronous motor based on deadbeat control using FPGA based hardware controller is proposed. Using the discrete time model of PMSM, the deadbeat control law is derived using a model inverse solution. The superior calculation capability of FPGA realize the ideal digital control feedback system without any sampling compensation method. The verification of the proposed method were carried out through simulations and experiments.
Impact of sarcopenia on biliary drainage during neoadjuvant therapy for pancreatic cancer
Kunio Kataoka,Eizaburo Ohno,Takuya Ishikawa,Kentaro Yamao,Yasuyuki Mizutani,Tadashi Iida,Hideki Takami,Osamu Maeda,Junpei Yamaguchi,Yukihiro Yokoyama,Tomoki Ebata,Yasuhiro Kodera,Hiroki Kawashima 대한소화기내시경학회 2024 Clinical Endoscopy Vol.57 No.1
Background/Aims: Since the usefulness of neoadjuvant chemo(radiation) therapy (NAT) for pancreatic cancer has been demonstrated, recurrent biliary obstruction (RBO) in patients with pancreatic cancer with a fully covered self-expandable metal stent (FCSEMS) during NAT is expected to increase. This study investigated the impact of sarcopenia on RBO in this setting. Methods: Patients were divided into normal and low skeletal muscle index (SMI) groups and retrospectively analyzed. Patient characteristics, overall survival, time to RBO (TRBO), stent-related adverse events, and postoperative complications were compared between the two groups. A Cox proportional hazard model was used to identify the risk factors for short TRBO. Results: A few significant differences were observed in patient characteristics, overall survival, stent-related adverse events, and postoperative complications between 38 patients in the normal SMI group and 17 in the low SMI group. The median TRBO was not reached in the normal SMI group and was 112 days in the low SMI group (p=0.004). In multivariate analysis, low SMI was the only risk factor for short TRBO, with a hazard ratio of 5.707 (95% confidence interval, 1.148–28.381; p=0.033). Conclusions: Sarcopenia was identified as an independent risk factor for RBO in patients with pancreatic cancer with FCSEMS during NAT.