Investigating the Impacts of Different Price-Based Demand Response Programs on Home Load Management

Rastegar, Mohammad,Fotuhi-Firuzabad, Mahmud,Choi, Jaeseok The Korean Institute of Electrical Engineers 2014 Journal of Electrical Engineering & Technology Vol.9 No.3

Application of residential demand response (DR) programs are currently realized up to a limited extent due to customers' difficulty in manually responding to the time-differentiated prices. As a solution, this paper proposes an automatic home load management (HLM) framework to achieve the household minimum payment as well as meet the operational constraints to provide customer's comfort. The projected HLM method controls on/off statuses of responsive appliances and the charging/discharging periods of plug-in hybrid electric vehicle (PHEV) and battery storage at home. This paper also studies the impacts of different time-varying tariffs, i.e., time of use (TOU), real time pricing (RTP), and inclining block rate (IBR), on the home load management (HLM). The study is effectuated in a smart home with electrical appliances, a PHEV, and a storage system. The simulation results are presented to demonstrate the effectiveness of the proposed HLM program. Peak of household load demand along with the customer payment costs are reported as the consequence of applying different pricings models in HLM.

A broadband Low Noise Amplifier with built-in linearizer in 0.13-@?m CMOS process

Rastegar, H.,Ryu, J.Y. Mackintosh Publications] 2015 Microelectronics Journal Vol.46 No.8

A linearized ultra-wideband (UWB) CMOS Low Noise Amplifier (LNA) is presented in this paper. The linearity performance is enhanced by exploiting PMOS-NMOS common-gate (CG) inverter as a built-in linearizer which leads to cancel out both the second- and third-order distortions. Two inductors are placed at the drain terminals of CG transistors in the built-in linearizer to adjust the phase and magnitude of the third-order distortion. A second-order band-pass Chebyshev filter is utilized in the input port of common-source (CS) configuration to provide broadband input matching at 3.1-10.6GHz frequency range to a 50-Ω antenna. Series and shunt peaking techniques are employed to extend the bandwidth (BW) and to flatten the gain response. Simulated in 0.13@?m CMOS technology, the CMOS LNA exhibits state of the art performance consuming 17.92mW of dc power. The CMOS LNA features a maximum gain of 10.24dB, 0.9-4.1dB noise figure (NF), and a third-order input intercept point (IIP3) of 6.8dBm at 6.3GHz.

An Integrated High Linearity CMOS Receiver Frontend for 24-GHz Applications

Rastegar, Habib,Ryu, Jee-Youl The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.5

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

A 2 GHz 20 dBm IIP3 Low-Power CMOS LNA with Modified DS Linearization Technique

Rastegar, Habib,Lim, Jae-Hwan,Ryu, Jee-Youl The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.4

The linearization technique for low noise amplifier (LNA) has been implemented in standard $0.18-{\mu}m$ BiCMOS process. The MOS-BJT derivative superposition (MBDS) technique exploits a parallel LC tank in the emitter of bipolar transistor to reduce the second-order non-linear coefficient ($g_{m2}$) which limits the enhancement of linearity performance. Two feedback capacitances are used in parallel with the base-collector and gate-drain capacitances to adjust the phase of third-order non-linear coefficients of bipolar and MOS transistors to improve the linearity characteristics. The MBDS technique is also employed cascode configuration to further reduce the second-order nonlinear coefficient. The proposed LNA exhibits gain of 9.3 dB and noise figure (NF) of 2.3 dB at 2 GHz. The excellent IIP3 of 20 dBm and low-power power consumption of 5.14 mW at the power supply of 1 V are achieved. The input return loss ($S_{11}$) and output return loss ($S_{22}$) are kept below - 10 dB and -15 dB, respectively. The reverse isolation ($S_{12}$) is better than -50 dB.

In situ formed nano-Ni catalytic effect on graphitization of phenolic resin (thermodynamic and microstructure investigation)

Rastegar H.,Mansorizadeh E. 한국탄소학회 2022 Carbon Letters Vol.32 No.3

In the present study, the effect of nickel nitrate addition as a catalytic precursor for the in situ formation of Ni nanoparticles during the heating process has been investigated on the modification of microstructure and graphitization of amorphous carbon resulting from pyrolysis of phenolic resin. For this purpose, the prepared resin samples were cured in carbon substrate with and without additives at temperatures of 800, 1000, and 1250 °C. XRD, FESEM, and TEM studies were performed to investigate the phase and microstructural changes in the samples during the heating process. In addition to phase and microstructural studies, thermodynamic calculations of the reactions performed for the in situ formation of nickel nanoparticles and their effective factors during the curing process were performed. The results indicated that nickel nitrate is transformed to nickel nanoparticles of different sizes during the reduction process in a reduced atmosphere. The in situ formation of nickel nanoparticles and its catalytic effect led to the graphitization of carbon resulting from the pyrolysis of phenolic resin at a temperature of 800 °C and above. By increasing temperature, the morphology of the formed graphite changed and hollow carbon nanotubes, carbon cells, and onion skin carbon were formed in the microstructure. It was also observed that by increasing the temperature and the amount of additive, carbon nanotubes and their size are increased. A noteworthy point from thermodynamic calculations during the formation of nickel nanoparticles was that the nickel nanoparticles themselves acted as accelerators of nickel oxide reduction reactions and the formation of nickel nanoparticles. This increases the amount of amorphous carbon graphitization resulting from the pyrolysis of phenolic resin which leads to the formation of more carbon nanotubes at higher temperatures.

First comprehensive report of bacteria spp. associated with cloaca of Laudakia nupta (Sauria: Agamidae) in Iran using molecular studies

Nasrullah Rastegar-Pouyani,Farkhondeh Sayyadi,Mehri Azadbakht,Khosrow Chehri 한국실험동물학회 2019 Laboratory Animal Research Vol.35 No.1

Iran bears a remarkable variety of reptiles. One of the lizard families occurring in Iran is the Family Agamidae which is widely are distributed throughout the old world. The large-scaled rock agamid, Laudakia nupta, is one of the well-known agamid. There are few reports of cloacal microbial on reptiles hence their function in cloacae remains unknown. Laudakia nupta usually live in rural and urban areas and close vicinity to man, they are likely to play an important role in the spread of disease that may be caused by these microorganisms and their transmission to man. Therefore, the aim of this study was to identify the bacterial flora colonizing the cloacal region of Laudakia nupta using molecular studies. The cloacal fluids were directly placed on nutrient agar (NA) plates and incubated at 25 ± 2 °C for 48 h. The resulting bacterial colonies were transferred to fresh nutrient agar (NA) plates for molecular studies. Twelve isolates were obtained from 17 specimens of Laudakia nupta. All bacteria isolates were identified as Bacillus subtillis (5), Bacillus cereus (4), Bacillus sp. (1), Pseudomonas putida (1), and Pseudomonas sp. (1) based on partial sequences of the 16 s rRNA gene. This is the first comprehensive report of bacteria spp. associated with cloaca of Laudakia nupta using molecular studies. In this research, we found that Laudakia nupta can be a carrier of bacteria which can transfer microorganisms to hosts.

Design of a CMOS Current-reuse LC VCO

Habib Rastegar,성명우,류지열 한국과학기술원 반도체설계교육센터 2018 IDEC Journal of Integrated Circuits and Systems Vol.4 No.1

This paper presents a cascode CMOS current-reuse voltage-controlled oscillator (LC VCO) for 24GHz automotive collision radar. This circuit is designed using 65nm CMOS technology. The VCO in modified current-reuse configuration where transistors are biased in subthreshold region to save power consumption. This scheme is utilized to simultaneously reduce the power consumption, and increase the transconductance and gain of the VCO circuit. The capacitive-feedback technique, including two series capacitors is also used to improve voltage swing of output ports under low power and low supply voltage conditions. This circuit also has fully-differential configuration to reduce RF noise and harmonic distortion. The proposed VCO showed phase noise of -123dBc/Hz at 1MHz offset, and power consumption of 321μW at power supply of 950mV with a FOM of -204 dBc/Hz. The die area occupied 0.35mm2.

A 2 GHz 20 dBm IIP3 Low-Power CMOS LNA with Modified DS Linearization Technique

Habib Rastegar,Jae-Hwan Lim,류지열 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.4

The linearization technique for low noise amplifier (LNA) has been implemented in standard 0.18-µm BiCMOS process. The MOS-BJT derivative superposition (MBDS) technique exploits a parallel LC tank in the emitter of bipolar transistor to reduce the second-order non-linear coefficient (gm2) which limits the enhancement of linearity performance. Two feedback capacitances are used in parallel with the base-collector and gate-drain capacitances to adjust the phase of third-order non-linear coefficients of bipolar and MOS transistors to improve the linearity characteristics. The MBDS technique is also employed cascode configuration to further reduce the second-order nonlinear coefficient. The proposed LNA exhibits gain of 9.3 dB and noise figure (NF) of 2.3 dB at 2 GHz. The excellent IIP3 of 20 dBm and low-power power consumption of 5.14 mW at the power supply of 1 V are achieved. The input return loss (S11) and output return loss (S22) are kept below -10 dB and -15 dB, respectively. The reverse isolation (S12) is better than -50 dB.

A High Linearity Ultra-Wide-Band (UWB) LNA

Habib Rastegar,Seong-Kyu Choi,Cheol-Hwan Kim,Myeong-U Sung,Shin-Gon Kim,Jae-Hwan Lim,Geun-Ho Choi,Jee-Youl Ryu,Seok-Ho Noh 한국정보기술학회 2014 Proceedings of KIIT Conference Vol.2014 No.5

An Integrated High Linearity CMOS Receiver Frontend for 24-GHz Applications

Habib Rastegar,Jee-Youl Ryu 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.5

Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS gm-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.