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A Charging Acceleration Technique for Highly Efficient Cascode Class-E CMOS Power Amplifiers
Ockgoo Lee,Jeonghu Han,Kyu Hwan An,Dong Ho Lee,Kun-Seok Lee,Songcheol Hong,Chang-Ho Lee IEEE 2010 IEEE journal of solid-state circuits Vol.45 No.10
<P>A cascode configuration in class-E CMOS power amplifiers (PAs) provides high reliability with respect to breakdown considerations. However, it causes a power loss due to the slow transition of a common-gate device from the triode region to the cut-off region. To minimize the power loss of cascode class-E CMOS PAs, we propose a charging acceleration technique, CAT. This method incorporates a capacitive element between the drain and the source of a common-gate device in a cascode configuration, accelerating the charging speed responsible for turning off a common-gate device instantly after a common-source device is turned off and thus minimizing power loss from the device. We compared the performance of the proposed cascode class-E PA to that of the conventional cascode class-E PA using a 0.18- CMOS process. With a 3.3-V power supply, the proposed fully-integrated CMOS PA achieves 30.7 dBm of maximum output power and 45.6% of power-added efficiency (PAE) with a dynamic range of 40 dB at 1.6 GHz. According to measurements, the proposed cascode class-E PA shows improvement in PAE over the conventional class-E PA of between 5% and 9% in a 1.5 to 2.0 GHz range.</P>
A High-Efficiency CMOS Power Amplifier Using 2:2 Output Transformer for 802.11n WLAN Applications
Lee, Ockgoo,Ryu, Hyunsik,Baek, Seungjun,Nam, Ilku,Jeong, Minsu,Kim, Bo-Eun The Institute of Electronics and Information Engin 2015 Journal of semiconductor technology and science Vol.15 No.2
A fully integrated high-efficiency linear CMOS power amplifier (PA) is developed for 802.11n WLAN applications using the 65-nm standard CMOS technology. The transformer topology is investigated to obtain a high-efficiency and high-linearity performance. By adopting a 2:2 output transformer, an optimum impedance is provided to the PA core. Besides, a LC harmonic control block is added to reduce the AM-to-AM/AM-to-PM distortions. The CMOS PA produces a saturated power of 26.1 dBm with a peak power-added efficiency (PAE) of 38.2%. The PA is tested using an 802.11n signal, and it satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieves -28-dB EVM at an output power of 18.6 dBm with a PAE of 14.7%.
A 60-GHz push-push InGaP HBT VCO with dynamic frequency divider
Lee, Ockgoo,Kim, Jeong-Geun,Lim, Kyutae,Laskar, J.,Hong, S. IEEE 2005 IEEE microwave and wireless components letters Vol.15 No.10
We present a 60-GHz push-push voltage-controlled oscillator (VCO) with dynamic frequency divider, which is implemented in an InGaP/GaAs heterojunction bipolar transistor technology. A common-base inductive feedback topology is used in the push-push VCO, which generates a pair of 30GHz differential outputs and a single-ended 60GHz push-push output. The 30GHz differential outputs are followed by the proposed dynamic frequency divider. The proposed dynamic frequency divider incorporates active loads with inductive peaking to achieve the higher bandwidth. The maximum operating frequency of the divider was found to be much higher than f<SUB>T</SUB>/2 of transistor. To the best of our knowledge, this is the first report demonstrating the extended bandwidth performance of the dynamic frequency divider with active loads and inductive peaking.
A High-Efficiency CMOS Power Amplifier Using 2:2 Output Transformer for 802.11n WLAN Applications
Ockgoo Lee,Hyunsik Ryu,Seungjun Baek,Ilku Nam,Minsu Jeong,Bo-Eun Kim 대한전자공학회 2015 Journal of semiconductor technology and science Vol.15 No.2
A fully integrated high-efficiency linear CMOS power amplifier (PA) is developed for 802.11n WLAN applications using the 65-nm standard CMOS technology. The transformer topology is investigated to obtain a high-efficiency and high-linearity performance. By adopting a 2:2 output transformer, an optimum impedance is provided to the PA core. Besides, a LC harmonic control block is added to reduce the AM-to-AM/AM-to-PM distortions. The CMOS PA produces a saturated power of 26.1 dBm with a peak power-added efficiency (PAE) of 38.2%. The PA is tested using an 802.11n signal, and it satisfies the stringent error vector magnitude (EVM) and mask requirements. It achieves ?28-dB EVM at an output power of 18.6 dBm with a PAE of 14.7%.
Review of Short-circuit Protection Circuits for SiC MOSFETs
Seungjik Lee,Ockgoo Lee,Ilku Nam 대한전자공학회 2023 Journal of semiconductor technology and science Vol.23 No.2
Silicon carbide (SiC) metal-oxide-semiconductor field effect transistors (MOSFETs) are commonly used in the power transistor industry owing to their superior conductivity, low switching loss, high-frequency operation, and desirable thermal characteristics. However, the short-circuit withstand time of SiC MOSFETs is shorter than that of Si devices, which is disadvantageous in fault states. Gate drivers for SiC MOSFETs require short-circuit protection and soft termination circuits to detect short circuits and protect the power devices and systems from a short-circuit state. Thus, short-circuit protection circuits for SiC MOSFETs are reviewed in this paper. Accordingly, short-circuit detection circuits classified according to gate-source voltage (VGS), drain-source voltage (VDS), and drain-source current (IDS) detection methods are discussed. Moreover, the merits and demerits of soft termination circuits are reviewed.
A 24 ㎓ CMOS Receiver Front-end for In-Cabin Radar Systems
Yangji Jeon,Suyeon Lee,Jinman Myung,Geonwoo Park,Seungjik Lee,Ockgoo Lee,Hyunwon Moon,Ilku Nam 대한전자공학회 2021 Journal of semiconductor technology and science Vol.21 No.4
A 24-㎓ direct-conversion receiver frontend is presented for in-cabin applications. The proposed RF receiver is composed of a low-noise amplifier, an I/Q down-conversion mixer, and an I/Q local oscillator (LO) generator circuit. An inverter - type transconductor with third-order nonlinearity cancellation is applied to the I/Q down-conversion mixer to improve the linearity of the I/Q down-conversion mixer. By adopting a linear I/Q down-conversion mixer and a balanced I/Q LO generator, the 24 ㎓ receiver front-end obtains high linearity and good I/Q balancing performance. The receiver front-end draws 21-㎃ current from a 1.2-V supply voltage. It shows a conversion gain of 30.4 ㏈, noise figure (NF) of 4.5 ㏈, and an input 1-㏈ compression point (input P1㏈) of -23 ㏈m in the 24-24.5 ㎓ range.
Younghyun Lim,Jeonghyun Lee,Yongsun Lee,Seong-Sik Song,Hong-Teuk Kim,Ockgoo Lee,Jaehyouk Choi Institute of Electrical and Electronics Engineers 2017 IEEE transactions on very large scale integration Vol.25 No.11
<P>An external capacitor-less ultra low-dropout (LDO) regulator that can continue to provide high power-supply rejection (PSR) over a wide range of the load current is proposed. Using the loop-gain stabilizer (LGS) to fix the dc level of the output voltage of the error amplifier to the optimal value, the LDO can keep maximizing the unity-gain frequency, while the load current changes widely up to 200 mA. Despite the multiple poles in the regulating loop, the stability can easily be obtained due to an intrinsic left-half plane zero, generated by the auxiliary path of the LGS. The proposed LDO was fabricated in a 40-nm CMOS process, and it had an input voltage of 1.1 V. When the dropout voltage was 0.1 V and the load current was 200 mA, the measured PSRs were -60 and -35 dB at 1 and 10 MHz, respectively. Due to the LGS, the dc loop gain was maintained to be high, resulting in good load and line regulations of 19 mu V/mA and 0.75 mV/V, respectively. While the total current consumption of the LDO was 275 mu A, the LGS consumed only 7 mu A. The area was 0.008 mm(2) with 4-pF on-chip capacitance for compensation.</P>
A TV Receiver Front-End With Linearized LNA and Current-Summing Harmonic Rejection Mixer
Im, Donggu,Lee, Ockgoo,Nam, Ilku IEEE 2017 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.64 No.3
<P>A low-noise and highly linear wideband receiver front-end composed of the linearized low noise amplifier and current-summing harmonic rejection mixer is implemented in a 0.18-mu m CMOS process for TV tuner applications. It shows a measured voltage gain (A(v)) of more than 34.5 dB, a noise figure of less than 3.5 dB, and a third-order input-referred intercept point (IIP3) of more than -20 dBm in the frequency range from 44 to 880 MHz. The baseband coefficient scaling and summation based on the current mirror ensure a third-and fifth-harmonic rejection ratio of over 45 dBc in measurement with high linearity performance. The power consumption of the proposed TV receiver front-end is 16.2 mW at a 1.8-V supply voltage.</P>
A Wideband Sub-㎓ Receiver Front-end Supporting High Sensitivity and Selectivity Mode
Ilku Nam,Ockgoo Lee,Donggu Im 대한전자공학회 2021 Journal of semiconductor technology and science Vol.21 No.4
A low noise and highly linear wideband RF front-end circuit for sub-㎓ Internet of Things (IoT) applications is proposed. The proposed frontend is composed of a broadband single-ended LNA, a wideband differential LNA employing thermal noise cancellation technique, and an in-phase and quadrature (I/Q) linearized harmonic rejection mixer (HRM). Depending on the interference environment, the proposed front-end supports two operation modes having high sensitivity and selectivity performance by enabling or disabling the first building block of the single-ended LNA. At high sensitivity mode, the frontend shows a voltage gain (Av) of greater than 38 ㏈, a noise figure (NF) of less than 2.1 ㏈, an input-referred third-order intercept point (IIP3) of greater than -23 ㏈m, and an input-referred second-order intercept point (IIP2) of greater than +15 ㏈m in the sub-㎓ frequency band. Concerning for high selectivity mode, it achieves an Av of greater than 22.5 ㏈, a NF of less than 4.7 ㏈, an IIP3 of greater than – 6.8 ㏈m, and an IIP2 of greater than +50 ㏈m over the same operating frequency range.
Bohun Shin,Changyeol Kim,Ockgoo Lee,So Ryoung Park,Sanguk Noh,Ilku Nam 대한전자공학회 2018 Journal of semiconductor technology and science Vol.18 No.4
A 24-GHz RF sensing receiver front-end with improved I/Q balanced LO generator is presented for a surveillance radar system. The proposed RF receiver front-end consists of a low-noise amplifier, an I/Q down-conversion mixer, and an I/Q local oscillator (LO) generator circuit. The proposed design method of a polyphase filter at millimeter-wave frequencies provides improved and balanced I/Q signals in comparison to a conventional polyphase filter. The receiver front-end draws 20-mA current from a 1.2-V supply voltage. The measured return loss of the RF input port is less than -10 dB in the range of 23.9–24.3 GHz. The receiver front-end achieves a conversion gain of 26.8 dB, noise figure (NF) of 5.1 dB, and an input 1-dB compression point (input P1dB) of -19.7 dBm in the 23.9–24.3 GHz range. Gain and phase mismatch between the I- and Q-paths at IF output are less than 0.15 dB and 0.3°, respectively.