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Impact of LDD Structure on Single-Poly EEPROM Characteristics
Kee-Yeol Na,Mun-Woo Rho,Kyung-Hoon Kim,Nam-Soo Kim,Yeong-Seuk Kim 한국정보과학회 1998 Journal of Electrical Engineering and Information Vol.3 No.3
The impact of LDD structure on the single-poly EEPROMs is investigated in this paper. The single-poly EEPROMs are fabricated using the 0.8㎛ CMOS ASIC process. The single-poly EEPROMs with LDD structure have slower program and erase speeds, but the drain and gate stresses and the endurance characteristics of these devices are much better than those of the single-poly EEPROMs with single-drain structure. The single-poly EEPROMs with LDD structure do not require the process modifications and need no additional masks, hence can be used for microprocessors and logic circuits with low-density and low-cost embedded EEPROMs.
Kee-Yeol Na,Yeong-Seuk Kim 한국물리학회 2009 Current Applied Physics Vol.9 No.1
In this paper, the improved characteristics of 10 V tolerant high-voltage n-channel lateral double diffused metal–oxide–semiconductor (LDMOS) devices, using a pure 0.25 lm standard low-voltage complementary metal–oxide–semiconductor (CMOS) logic process with dual gate oxide, are described. The fabricated transistors showed about 30% better current driving characteristics and about 40% higher drain operating voltage than previous reports of these kinds of devices. The transistors maintained a breakdown voltage, BVDSS, over 14 V. These devices also showed good sub-threshold characteristics. This paper describes the cost-effective and high performance n-channel high-voltage LDMOS using a pure low-voltage standard CMOS logic process. In this paper, the improved characteristics of 10 V tolerant high-voltage n-channel lateral double diffused metal–oxide–semiconductor (LDMOS) devices, using a pure 0.25 lm standard low-voltage complementary metal–oxide–semiconductor (CMOS) logic process with dual gate oxide, are described. The fabricated transistors showed about 30% better current driving characteristics and about 40% higher drain operating voltage than previous reports of these kinds of devices. The transistors maintained a breakdown voltage, BVDSS, over 14 V. These devices also showed good sub-threshold characteristics. This paper describes the cost-effective and high performance n-channel high-voltage LDMOS using a pure low-voltage standard CMOS logic process.
A Novel Single Polysilicon EEPROM Cell With a Polyfinger Capacitor
Na, Kee-Yeol,Kim, Young-Sik,Kim, Yeong-Seuk IEEE 2007 IEEE electron device letters Vol.28 No.11
<P> In this letter, we describe a novel single polysilicon electrically erasable read-only memory cell with polyfinger capacitor for the control gate (CG). A finger-type capacitor structure with <TEX>$\hbox{CoSi}_{2}$</TEX> is applied to a floating gate and the CG of the proposed cell. The proposed cell is fabricated by using a 0.18-<TEX>$\mu\hbox{m}$</TEX> standard logic process. The intergate dielectrics of the proposed cell are formed by a conventional lightly doped drain spacer material that is composed of <TEX>$\hbox{SiO}_{2}$</TEX> and <TEX>$\hbox{Si}_{3}\hbox{N}_{4}$</TEX> to avoid any process modification. A Fowler–Nordheim tunneling method is applied for the programming and erasing of the cell. Endurance characteristics of up to 120 000 cycles are demonstrated. The proposed cell shows acceptable data retention characteristics. </P>
Impact of LDD Structure on Single-Poly EEPROM Characteristics
Na, Kee-Yeol,Park, Mun-Woo,Kim, Kyung-Hoon,Kim, Nan-Soo,Kim, Yeong-Seuk The Korean Institute of Electrical Engineers 1998 Journal of Electrical Engineering and Information Vol.3 No.3
The impact of LDD structure on the single-poly EEPROMs is investigated in this paper. The single-poly EEPROMs are fabricated using the 0.8$\mu\textrm{m}$ CMOS ASIC process. The single-poly EEPROMs with LDD structure have slower program and erase speeds, but the drain and gate stresses and the endurance characteristics of these devices are much better than those of the single-poly EEPROMs with single-drain structure. The single-poly EEPROMs with LDD structure do not require the process modifications and need no additional masks, hence can be used for microprocessors and logic circuits with low-density and low-cost embedded EEPROMs.
Kee-Yeol Na,Ki-Ju Baek,Jun-Kyu Kim,Dongwon Kim,Nam-Soo Kim,Yeong-Seuk Kim Institute of Electrical and Electronics Engineers 2014 IEEE transactions on electron devices Vol. No.
<P>An n-channel MOSFET with lateral asymmetric substrate doping (LASD) is presented in this paper. The proposed LASD device has a p-well on the source side and a p-substrate on the drain side. The LASD MOSFET was designed by the simple p-well layout approach and fabricated using the 0.18 μm standard low-voltage CMOS process without any process modification. The experimental measurements showed the improved analog performances of the LASD MOSFET: higher transconductance (gm), lower drain conductance (gds), lower drain induced barrier lowering, higher transconductance generation factor (gm/I<SUB>D</SUB>), and higher Early voltage (V<SUB>EA</SUB>). In addition, the LASD device showed strong body-effect immunity: smaller V<SUB>T</SUB> shift according to body bias and lower body bias sensitivity factor (gmb/gm).</P>
N-Channel Dual-Workfunction-Gate MOSFET for Analog Circuit Applications
Kee-Yeol Na,Ki-Ju Baek,Yeong-Seuk Kim IEEE 2012 IEEE transactions on electron devices Vol.59 No.12
<P>Analog behaviors of n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with dual-workfunction-gate (DWFG) structure are presented. The gate of the n-channel DWFG MOSFET is composed of p<SUP>+</SUP> and n<SUP>+</SUP> poly-Si along the channel carrier flowing direction. To investigate the impact of the proportional length of p- and n-type-doped poly-Si on analog behaviors, they are varied within a total physical gate length of 1.0 μm. Various dc characteristics that directly affect analog circuit performances are evaluated from the fabricated devices: <I>I</I>-<I>V</I> characteristics, drain-induced barrier lowering, transconductance (<I>gm</I>), drain conductance (<I>g</I><SUB>ds</SUB> = 1/<I>r</I><SUB>out</SUB>), intrinsic gain (<I>AV</I> = <I>gm</I>/<I>g</I><SUB>ds</SUB>), and Early voltage (<I>V</I><SUB>EA</SUB> = <I>ID</I>/<I>g</I><SUB>ds</SUB>). From the measurements, the DWFG devices always show improved characteristics over conventional devices (n<SUP>+</SUP>-doped poly-Si gate). The DWFG device with the shortest p<SUP>+</SUP> poly-Si gate length (<I>p</I>/<I>n</I> = 0.4/0.6) shows better <I>gm</I> characteristics than other DWFG devices. The <I>g</I><SUB>ds</SUB> characteristics of the fabricated DWFG devices are improved as the length of the p<SUP>+</SUP> poly-Si increases. The best <I>AV</I> and <I>V</I><SUB>EA</SUB> are taken from the device with a p-type-doped poly-Si length of 0.7 μm (<I>p</I>/<I>n</I> = 0.7/0.3).</P>
High-Voltage LDMOS Transistor With Split-Gate Structure for Improved Electrical Performance
Kee-Yeol Na,Ki-Ju Baek,Gun-Woong Lee,Yeong-Seuk Kim IEEE 2013 IEEE transactions on electron devices Vol.60 No.10
<P>An n-channel split-gate laterally double-diffused metal-oxide-semiconductor (LDMOS) device is presented. The proposed split-gate LDMOS has a primary gate (PG) and floating gate (FG). The FG is formed by spacer etching and placed along the perimeter of the PG. The potential of the FG is determined by the potential of the PG and the capacitive coupling ratio. Therefore, the FG has lower potential than that of the PG. This potential difference along the channel length direction accelerates channel carriers, which ultimately enhances device performances. From device measurements, the fabricated splitgate LDMOS devices showed improved electrical characteristics: lower drain-induced barrier lowering; higher transconductance (g<SUB>m</SUB>); lower drain conductance (g<SUB>ds</SUB> = 1/<SUB>rout</SUB>); lower ON-resistances R<SUB>ON</SUB>; and higher early voltage V<SUB>EA</SUB> = I<SUB>D</SUB>/g<SUB>ds</SUB>.</P>
이중 일함수 게이트 구조를 갖는 CMOS 소자의 전기적 특성
나기열(Kee-Yeol Na),신윤수(Yoon-Soo Shin),김영식(Young-Sik Kim),이광규(Kwang-Kyu Lee),최홍규(Hong-Kyu Choi),김성준(Sungjoon Kim),김영석(Yeong-Seuk Kim) 대한전자공학회 2006 대한전자공학회 학술대회 Vol.2006 No.11
This paper discusses silicon complementary metal-oxide-semiconductor (CMOS) field-effect transistors with dual work function gates (DWFG) to improve transconductance (gm) and drain conductance (gds) characteristics. For a n-channel metal-oxide-semiconductor field effect transistor (MOSFET) device, the poly-silicon gate on the source and drain side are doped p+ and n+, respectively and vice versa for a p-channel MOSFET. The work function difference in a poly-silicon gate affects channel potential distribution and increases the lateral electric field inside the channel. The increased electric field inside the channel improves carrier drift velocity. Experimental results from the fabricated DWFG devices show improved gm and gds over conventional single work function gate devices.