Development of a Mobile Application, "Wild Flowers of Bukhansan National Park (version 1.0)", for Identification of Plants in Bukhansan National Park

Kim, Sang-Tae,Lee, Seung-Yeon,Kim, Seung-Chul,Byun, Hye-Won,Lee, Sang-Tae,Kim, Mu-Yeal,Hong, Seok-Pyo,Chung, Young-Jae,Park, Ki-Ryong,Lee, Chung-Hee,Lee, Joong-Ku,Heo, Kyeong-In,Lee, Ji-Ye,Lee, Eun-Je National Science Museum of Korea 2011 Journal of Korean nature Vol.4 No.3

We developed the educational purpose mobile application, named "Wild Flowers of Bukhansan National Park (version 1.0)", aiming for easy identification of wild flowers for students and visitors in the park. When visitors find a flower or part of plant in the park, visitors can search for its name utilizing the pictures and characters provided in their own smartphone mobile devices or tablet PCs. The application provides pictures of wild flowers in the park and character-based searching system based on 12 diagnostic features (e.g., growth form, leaf arrangement, flower symmetry, petal color, petal number, sepal number, etc). We adopted the complete floristic survey of Chung and Lee (1962) and added species that we confirmed their distribution in the park during the development of this application. In summary, number of vascular plants in this park was estimated to be 428 taxa including 100 families, 280 genera, 327 species, 1 subspecies, 50 varieties, and 5 formas. We provided a total of 588 pictures representing 358 taxa and each taxon includes multiple pictures in many cases. Included identification quizzes can be an efficient educational tool as well as fun activity for students and visitors who are learning plant species in Korea. Our next step will include GPS function in the application for indicating visitor's location and for providing previously reported sites of the species that we interested in the map of the park. The future application which includes GPS function will be a valuable tool for the monitoring of rare plants, plant researches related to the climate changes, etc. We currently provide Korean iPhone version only, and English version and both of android versions will be serviced soon.

UHF RFID 태그 칩용 저전력 EEPROM설계

이원재,이재형,박경환,이정환,임규호,강형근,고봉진,박무훈,하판봉,김영희,Yi, Won-Jae,Lee, Jae-Hyung,Park, Kyung-Hwan,Lee, Jung-Hwan,Lim, Gyu-Ho,Kang, Hyung-Geun,Ko, Bong-Jin,Park, Mu-Hun,Ha, Pan-Bong,Kim, Young-Hee 한국정보통신학회 2006 한국정보통신학회논문지 Vol.10 No.3

본 논문에서 는 플래쉬 셀을 사용하여 수동형 UHF RFID 태그 칩에 사용되는 저전력 1Kb 동기식 EEPROM을 설계하였다. 저전력 EEPROM을 구현하기 위한 방법으로 다음과 같은 4가지 방법을 제안하였다. 첫째, VDD(=1.5V)와 VDDP(=2.5V)의 이중 전원 공급전압 방식을 사용하였고, 둘째, 동기식 회로 설계에서 클럭(clock) 신호가 계속 클럭킹(clocking)으로 인한 스위칭 전류(switching current)가 흐르는 것을 막기 위해 CKE(Clock Enable) 신호를 사용하였다. 셋째, 읽기 사이클에서 전류 센싱(current sensing) 방식 대신 저전력 소모를 갖는 clocked inverter를 사용한 센싱 방식을 사용하였으며, 넷째, 쓰기 모드시 Voltage-up 변환기(converter) 회로를 사용하여 기준전압 발생기(Reference Voltage Generator)에는 저전압인 VDD를 사용할 수 있도록 하여 전력 소모를 줄일 수가 있었다. $0.25{\mu}m$ EEPROM 공정을 이용하여 칩을 제작하였으며, 1Kb EEPROM을 설계한 결과 읽기 모드와 쓰기 모드 시에 소모되는 전력은 각각 $4.25{\mu}W$와 $25{\mu}W$이고, 레이아웃 면적(layout area)은 $646.3\times657.68{\mu}m^2$이다. In this paper, a low-power 1Kb synchronous EEPROM is designed with flash cells for passive UHF RFID tag chips. To make a low-power EEPROM, four techniques are newly proposed. Firstly, dual power supply voltages VDD(1.5V) and VDDP(2.5V), are used. Secondly, CKE signal is used to remove switching current due to clocking of synchronous circuits. Thirdly, a low-speed but low-power sensing scheme using clocked inverters is used instead of the conventional current sensing method. Lastly, the low-voltage, VDD for the reference voltage generator is supplied by using the Voltage-up converter in write cycle. An EEPROM is fabricated with the $0.25{\mu}m$ EEPROM process. Simulation results show that power dissipations are $4.25{\mu}W$ in the read cycle and $25{\mu}W$ in the write cycle, respectively. The layout area is $646.3\times657.68{\mu}m^2$.

UHF RFID 태그 칩용 저전력, 저면적 비동기식 EEPROM 설계

백승면,이재형,송성영,김종희,박문훈,하판봉,김영희,Baek, Seung-Myun,Lee, Jae-Hyung,Song, Sung-Young,Kim, Jong-Hee,Park, Mu-Hun,Ha, Pan-Bong,Kim, Young-Hee 한국정보통신학회 2007 한국정보통신학회논문지 Vol.11 No.12

본 논문에서는 $0.18{\mu}m$의 EEPROM cell을 사용하여 수동형 UHF RFID 태그 칩에 사용되는 저전력, 저면적의 1Kbits 비동기식 EEPROM IP를 설계하였다. 저면적 회로 설계 기술로는 $0.18{\mu}m$ EEPROM 공정을 이용하여 비동기식 EEPROM IP를 설계하므로 command buffer와 address buffer를 제거하였고 separate I/O 방식을 사용하므로 tri-state 데이터 출력 버퍼(data output buffer)를 제거하였다. 그리고 저전압(low voltage)의 VDD에서 EEPROM cell이 필요로 하는 고전압(high voltage)인 VPP와 VPPL 전압을 안정적으로 공급하기 위해 기존의 PN 접합 다이오드 대신 Schottky 다이오드를 사용한 Dickson 전하펌프를 설계하므로 전하펌프의 펌핑단(pumping stage)의 수를 줄여 전하펌프가 차지하는 면적을 줄였다. 저전력 회로 설계 기술로 Dickson 전하 펌프(charge pump)를 이용하여 VPP generator를 만들고 Dickson 전하펌프의 임의의 노드 전압을 이용하여 프로그램과 지우기 모드에서 각각 필요로 하는 VPPL 전압을 선택하도록 하게 해주는 VPPL 전원 스위칭 회로를 제안하여 쓰기전류(write current)를 줄이므로 저전력 EEPROM IP를 구현하였다. $0.18{\mu}m$ 공정을 이용하여 설계된 비동기식 EEPROM용 테스트 칩은 제작 중에 있으며, 비동기식 1Kbits EEPROM의 레이아웃 면적은 $554.8{\times}306.9{\mu}m2$로 동기식 1Kbits EEPROM에 비해 레이아웃면적을 11% 정도 줄였다. In this paper, a low-power and small-area asynchronous 1 kilobit EEPROM for passive UHF RFID tag chips is designed with $0.18{\mu}m$ EEPROM cells. As small area solutions, command and address buffers are removed since we design asynchronous I/O interface and data output buffer is also removed by using separate I/O. To supply stably high voltages VPP and VPPL used in the cell array from low voltage VDD, Dickson charge pump is designed with schottky diodes instead of a PN junction diodes. On that account, we can decrease the number of stages of the charge pump, which can decrease layout area of charge pump. As a low-power solution, we can reduce write current by using the proposed VPPL power switching circuit which selects each needed voltage at either program or write mode. A test chip of asynchronous 1 kilobit EEPROM is fabricated, and its layout area is $554.8{\times}306.9{\mu}m2$., 11% smaller than its synchronous counterpart.

포톤 계수 방식의 $32{\times}32$ 픽셀 어레이를 갖는 디지털 CMOS X-ray 이미지 센서 설계

성관영,김태호,황윤금,전성채,진승오,허영,하판봉,박무훈,김영희,Sung, Kwan-Young,Kim, Tae-Ho,Hwang, Yoon-Geum,Jeon, Sung-Chae,Jin, Seung-Oh,Huh, Young,Ha, Pan-Bong,Park, Mu-Hun,Kim, Young-Hee 한국정보통신학회 2008 한국정보통신학회논문지 Vol.12 No.7

본 논문에서는 $0.18{\mu}m$ triple-well CMOS 공정을 사용하여 포톤계수 방식의 $32{\times}32$ 픽셀 어레이를 갖는 CMOS ray 영상센서를 설계하였다. 설계된 영상센서의 카픽셀은 $100{\times}100\;{\mu}m2$ 면적을 가지고 있고 약 400개의 트랜지스터로 구성되어 있으며, 범프 본딩을 통해 ray 검출기와 CSA(Charge Sensitive Amplifier)의 연결을 위한 $50{\times}50{\mu}m2$의 오픈패드를 가지고 있다. 각각의 싱글픽셀 CSA에서 전압 바이어스 회로를 사용한 folded cascode CMOS OP amp 대신 레이아웃 면적을 줄이기 위하여 self biased folded cascode CMOS OP amp를 이용하였으며, 계수 모드 진입 전후에 CLK에서 발생 할 수 있는 short pulse를 제거하는 15bit LFSR 계수기 (Linear Feedback Shift Register Counter) 클럭 발생회로를 제안하였으며, 읽기 모드에서 CMOS X-ray 영상센서의 최대 전류를 줄이기 위하여 열 어드레스 디코더를 이용하여 한 열씩 읽도록 설계하였다. In this paper, x-ray image sensor of photon counting type having a $32{\times}32$ pixel array is designed with $0.18{\mu}m$ triple-well CMOS process. Each pixel of the designed image sensor has an area of loot $100{\times}100\;{\mu}m2$ and is composed of about 400 transistors. It has an open pad of an area of $50{\times}50{\mu}m2$ of CSA(charge Sensitive Amplifier) with x-ray detector through a bump bonding. To reduce layout size, self-biased folded cascode CMOS OP amp is used instead of folded cascode OP amp with voltage bias circuit at each single-pixel CSA, and 15-bit LFSR(Linear Feedback Shift Register) counter clock generator is proposed to remove short pulse which occurs from the clock before and after it enters the counting mode. And it is designed that sensor data can be read out of the sensor column by column using a column address decoder to reduce the maximum current of the CMOS x-ray image sensor in the readout mode.

MCU용 Fast 256Kb EEPROM 설계

김용호,박헌,박무훈,하판봉,김영희,Kim, Yong-Ho,Park, Heon,Park, Mu-Hun,Ha, Pan-Bong,Kim, Young-Hee 한국정보통신학회 2015 한국정보통신학회논문지 Vol.19 No.3

본 논문에서는 MCU(Micro Controller Unit) IC를 위한 50ns 256Kb EEPROM 회로를 설계하였다. 설계된 EEPROM IP는 기준전압을 이용한 차동증폭기 형태의 DB(Data Bus) 센싱 회로를 제안하여 읽기 동작시 데이터 센싱 속도를 빠르게 하였으며, DB를 8등분한 Distributed DB 구조를 적용하여 DB의 기생 커패시턴스 성분을 줄여 DB의 스위칭 속도를 높였다. 또한 기존의 RD 스위치 회로에서 5V 스위치 NMOS 트랜지스터를 제거함으로써 읽기 동작 시 BL의 프리차징 시간을 줄여 액세스 시간을 줄였고 데이터 센싱 시 DB 전압과 기준전압 간의 전압차 ${\Delta}V$를 0.2VDD 정도 확보하여 출력 데이터의 신뢰도를 높였다. 매그나칩반도체 $0.18{\mu}m$ EEPROM 공정으로 설계된 256Kb EEPROM IP의 액세스 시간은 45.8ns 이며 레이아웃 면적은 $1571.625{\mu}m{\times}798.540{\mu}m$이다. In this paper, a 50ns 256-kb EEPROM IP for MCU (micro controller unit) ICs is designed. The speed of data sensing is increased in the read mode by using a proposed DB sensing circuit of differential amplifier type which uses the reference voltage, and the switching speed is also increased by reducing the total DB parasitic capacitance as a distributed DB structure is separated into eight. Also, the access time is reduced reducing a precharging time of BL in the read mode removing a 5V NMOS transistor in the conventional RD switch, and the reliability of output data can be secured by obtaining the differential voltage (${\Delta}V$) between the DB and the reference voltages as 0.2*VDD. The access time of the designed 256-kb EEPROM IP is 45.8ns and the layout size is $1571.625{\mu}m{\times}798.540{\mu}m$ based on MagnaChip's $0.18{\mu}m$ EEPROM process.

The Protective Effect of Chlorophyll a Against Oxidative Stress and Inflammatory Processes in LPS-stimulated Macrophages

Park, Ji-Young,Park, Chung-Mu,Kim, Jin-Ju,Noh, Kyung-Hee,Cho, Chung-Won,Song, Young-Sun Korean Society of Food Science and Technology 2007 Food Science and Biotechnology Vol.16 No.2

This study was designed to investigate the suppressive effect of chlorophyll a on nitric oxide (NO) production and intracellular oxidative stress. In addition, chlorophyll a regulation of nuclear factor (NF) ${\kappa}B$ activation and inducible NO synthase (iNOS) expression were explored as potential mechanisms of NO suppression in a lipopolysaccharide (LPS)-stimulated macrophage cell line. RAW 264.7 murine macrophages were preincubated with various concentrations ($0-10\;{\mu}g/ mL$) of chlorophyll a and stimulated with LPS to induce oxidative stress and inflammatory response. Treatment with chlorophyll a reduced the accumulation of thiobarbituric acid-reactive substances (TBARS), enhancing glutathione level and the activities of antioxidative enzymes including superoxide dismutase, catalase, glutathione peroxidase (GSH-px), and glutathione reductase in LPS-stimulated macrophages compared to LPS-only treated cells. NO production was significantly suppressed in a dose-dependent manner (p<0.05) with an $IC_{50}$ of $12.8\;{\mu}g/mL$. Treatment with chlorophyll a suppressed the levels of iNOS protein and its mRNA expression. The specific DNA binding activities of NFkB on nuclear extracts from chlorophyll a treated cells were significantly suppressed in a dose-dependent manner with an $IC_{50}$ of $10.7\;{\mu}g/mL$. Chlorophyll a ameliorates NO production and iNOS expression through the down-regulation of NFkB activity, which may be mediated by attenuated oxidative stress in RAW 264.7 macrophages.

Morin Protects Acute Liver Damage by Carbon Tetrachloride ($CCl_4$) in Rat

Lee, Hee-Seung,Jung, Kyung-Hee,Hong, Sang-Won,Park, In-Sub,Lee, Chong-Mu,Han, Hyo-Kyung,Lee, Don-Haeng,Hong, Soon-Sun 대한약학회 2008 Archives of Pharmacal Research Vol.31 No.9

The purpose of this study was to investigate possible beneficial effects of morin on $CCl_4$-induced acute hepatotoxicity in rats. Rats received a single dose of $CCl_4$ ($150{\mu}L$/100 g 1:1 in corn oil). Morin treatment (20 mg/kg) was given at 48, 24, and 2 h before $CCl_4$ administration. $CCl_4$ challenge elevated serum alanine transaminase (ALT), aspartate transaminase (AST), and alkaline phosphatase (ALP) levels, but these effects were prevented by the pretreatment of rats with morin. To identify the mechanism of protective activity of morin in $CCl_4$-induced hepatotoxicity in rats, we investigated expressions of tumor necrosis factor alpha (TNF-$\alpha$), interleukin-$1{\beta}$ (IL-$1{\beta}$), interleukin-6 (IL-6), and inducible nitric oxide (iNOS). The expressions of TNF-$\alpha$, IL-$1{\beta}$, IL-6, and iNOS were increased by $CCl_4$ treatment and increased expressions of those were decreased by morin. These findings suggest that morin prevents acute liver damage by inhibiting the production of TNF-$\alpha$, IL-$1{\beta}$, IL-6, and iNOS.

넓은 전압 범위와 개선된 파워-업 특성을 가지는 밴드갭 기준전압 발생기의 스타트-업 회로

성관영,김종희,김태호,카오투안부,이재형,임규호,박무훈,하판봉,김영희,Sung, Kwang-Young,Kim, Jong-Hee,Kim, Tae-Ho,Vu, Cao Tuan,Lee, Jae-Hyung,Lim, Gyu-Ho,Park, Mu-Hum,Ha, Pan-Bong,Kim, Young-Hee 한국정보통신학회 2007 한국정보통신학회논문지 Vol.11 No.8

본 논문에서는 넓은 동작전압 범위와 저소비 전력 그리고 개선된 파워-업 특성을 가지는 캐스코드 전류 거울형 CMOS 밴드갭 기준전압 발생기의 스타트-업 회로를 제안하였다. 새롭게 제안된 스타트-업 회로는 기존의 스타트-업 회로에 비해 안정적인 파워-업 특성을 가지며 공급전압(VDDA)이 높아지더라도 밴드갭 기준전압 발생기 회로의 동작에 영향을 미치지 않는 것을 모의실험을 통하여 확인하였고 $0.18{\mu}m$ tripple-well CMOS 공정을 이용하여 테스트 칩을 제작하고 측정하였다. 측정 된 기준전압 Vref는 평균값이 738mV이고 $3{\sigma}$는 29.88mV이다. A start-up circuit of the bandgap reference voltage generator of cascode current mirror type with wide operating voltage range and enhanced power-up characteristics is proposed in the paper. It is confirmed by simulation that the newly proposed start-up circuit does not affect the operation of the bandgap reference voltage generatory even though the supply voltage(VDDA) is higher and has more stable power-up characteristic than the conventional start-up circuit. Test chips are designed and fabricated with $0.18{\mu}m$ tripple well CMOS process and their test has been completed. The mean value of measured the reference voltage(Vref) is 738mV and The three sigma value($3{\sigma}$) is 29.88mV.

저전압 SoC용 밴드갭 기준 전압 발생기 회로 설계

이태영,이재형,김종희,심외용,김태훈,박무훈,하판봉,김영희,Lee, Tae-Young,Lee, Jae-Hyung,Kim, Jong-Hee,Shim, Oe-Yong,Kim, Tae-Hoon,Park, Mu-Hun,Ha, Pan-Bong,Kim, Young-Hee 한국정보통신학회 2008 한국정보통신학회논문지 Vol.12 No.1

The band-gap reference voltage generator which can be operated by low voltage is proposed in this paper. The proposed BGR circuit can be realized in logic process by using parasitic NPN BJTs because a $Low-V_T$ transistors are not necessary. The proposed BGR circuit is designed and fabricated using $0.18{\mu}m$ triple-well process. The mean voltage of measured VREF is 0.72V and the three sigma$(3{\sigma})$ is 45.69mv. 본 논문에서는 $Low-V_T$ 트랜지스터가 필요 없는 로직공정으로 Parasitic NPN BJT를 이용하여 저 전압에서 동작 가능한 밴드갭 기준전압 발생기 회로를 제안하였다. $0.18{\mu}m$ triple-well 공정을 사용한 BGR회로를 측정 한 결과 VREF의 평균전압은 0.72V $3{\sigma}$는 45.69mV로 양호하게 측정되었다.

동기식 256-bit OTP 메모리 설계

이용진,김태훈,심외용,박무훈,하판봉,김영희,Li, Long-Zhen,Kim, Tae-Hoon,Shim, Oe-Yong,Park, Mu-Hun,Ha, Pan-Bong,Kim, Young-Hee 한국정보통신학회 2008 한국정보통신학회논문지 Vol.12 No.7

In this paper is designed a 256-bit synchronous OTP(one-time programmable) memory required in application fields such as automobile appliance power ICs, display ICs, and CMOS image sensors. A 256-bit synchronous memory cell consists of NMOS capacitor as antifuse and access transistor without a high-voltage blocking transistor. A gate bias voltage circuit for the additional blocking transistor is removed since logic supply voltage VDD(=1.5V) and external program voltage VPPE(=5.5V) are used instead of conventional three supply voltages. And loading current of cell to be programmed increases according to RON(on resistance) of the antifuse and process variation in case of the voltage driving without current constraint in programming. Therefore, there is a problem that program voltage can be increased relatively due to resistive voltage drop on supply voltage VPP. And so loading current can be made to flow constantly by using the current driving method instead of the voltage driving counterpart in programming. Therefore, program voltage VPP can be lowered from 5.9V to 5.5V when measurement is done on the manufactured wafer. And the sens amplifier circuit is simplified by using the sens amplifier of clocked inverter type instead of the conventional current sent amplifier. The synchronous OTP of 256 bits is designed with Magnachip $0.13{\mu}m$ CMOS process. The layout area if $298.4{\times}314{\mu}m2$. 본 논문에서는 자동차 전장용 Power IC, 디스플레이 구동 칩, CMOS 이미지 센서 등의 응용분야에서 필요로 하는 동기식 256-bit OTP(one-time programmable) 메모리를 설계하였다. 동기식 256-bit OTP 메모리의 셀은 고전압 차단 트랜지스터 없이 안티퓨즈인 NMOS 커패시터와 액세스 트랜지스터로 구성되어 있다. 기존의 3종류의 전원 전압을 사용하는 대신 로직 전원 전압인 VDD(=1.5V)와 외부 프로그램 전압인 VPPE(=5.5V)를 사용하므로 부가적인 차단 트랜지스터의 게이트 바이어스 전압 회로를 제거하였다. 그리고 프로그램시 전류 제한 없이 전압 구동을 하는 경우 안티퓨즈의 ON 저항 값과 공정 변동에 따라 프로그램 할 셀의 부하 전류가 증가한다. 그러므로 프로그램 전압은 VPP 전원 선에서의 저항성 전압 감소로 인해 상대적으로 증가하는 문제가 있다. 그래서 본 논문에서는 전압 구동 대신 전류 구동방식을 사용하여 OTP 셀을 프로그램 할 때 일정한 부하전류가 흐르게 한다. 그래서 웨이퍼 측정 결과 VPPE 전압은 5.9V에서 5.5V로 0.4V 정도 낮출 수 있도록 하였다. 또한 기존의 전류 감지 증폭기 대신 Clocked 인버터를 사용한 감지 증폭기를 사용하여 회로를 단순화시켰다. 동기식 256-bit OTP IP는 매그나칩 반도체 $0.13{\mu}m$ 공정을 이용하여 설계하였으며, 레이아웃 면적은 $298.4{\times}3.14{\mu}m2$이다.