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Design of Low-Cost Transimpedance Amplifier for Optical Receiver
Mohammad Marufuzzaman,Mamun Bin Ibne Reaz,Lye Suet Yeng,Labonnah Farzana Rahman,Torikul Islam Badal 한국전기전자재료학회 2018 Transactions on Electrical and Electronic Material Vol.19 No.1
The transimpedance amplifi er (TIA) is the most favorable and effi cient choice for the front-end preamplifi er in optical fi bercommunication systems. High gain and low input noise to amplify weak and susceptible input signals are the two majoradvantages of TIAs. Moreover, to realize a low-cost solution, a TIA should be implemented in a complementary metal-oxidesemiconductor (CMOS) process and should occupy a small area. This paper presents a low-cost TIA for optical receiversin a 180-nm CMOS process. The proposed TIA combines both open-loop and closed-loop topologies. A capacitance isolationmethod is used for noise and bandwidth optimization. Finally, capacitive peaking is used for bandwidth enhancement. Moreover, the proposed TIA is designed without using any inductors for bandwidth enhancement as well as for reducingchip area. Simulation results show that the proposed TIA works up to a frequency of 2.2 GHz with a transimpedance gainof 54.4 dBΩ. The TIA consumes only 19.7 mW with a supply voltage of 1.8 V, and the active area of the proposed circuitis only 0.003 mm 2 .
Low Dropout Voltage Regulator Using 130 nm CMOS Technology
Marufuzzaman, Mohammad,Reaz, Mamun Bin Ibne,Rahman, Labonnah Farzana,Mustafa, Norhaida Binti,Farayez, Araf The Korean Institute of Electrical and Electronic 2017 Transactions on Electrical and Electronic Material Vol.18 No.5
In this paper, we present the design of a 4.5 V low dropout (LDO) voltage regulator implemented in the 130 nm CMOS process. The design uses a two-stage cascaded operational transconductance amplifier (OTA) as an error amplifier, with a body bias technique for reducing dropout voltages. PMOS is used as a pass transistor to ensure stable output voltages. The results show that the proposed LDO regulator has a dropout voltage of 32.06 mV when implemented in the130 nm CMOS process. The power dissipation is only 1.3593 mW and the proposed circuit operates under an input voltage of 5V with an active area of $703{\mu}m^2$, ensuring that the proposed circuit is suitable for low-power applications.
Low Dropout Voltage Regulator Using 130 nm CMOS Technology
Mohammad Marufuzzaman,Mamun Bin Ibne Reaz,Labonnah Farzana Rahman,Norhaida Binti Mustafa,Araf Farayez 한국전기전자재료학회 2017 Transactions on Electrical and Electronic Material Vol.18 No.5
In this paper, we present the design of a 4.5 V low dropout (LDO) voltage regulator implemented in the 130 nm CMOS process. The design uses a two-stage cascaded operational transconductance amplifier (OTA) as an error amplifier, with a body bias technique for reducing dropout voltages. PMOS is used as a pass transistor to ensure stable output voltages. The results show that the proposed LDO regulator has a dropout voltage of 32.06 mV when implemented in the130 nm CMOS process. The power dissipation is only 1.3593 mW and the proposed circuit operates under an input voltage of 5V with an active area of 703 μm<sup>2</sup>, ensuring that the proposed circuit is suitable for low-power applications.
Sudipta Chowdhury,Mohammad Marufuzzaman,Huseyin Tunc,Linkan Bian,William Bullington 한국CDE학회 2019 Journal of computational design and engineering Vol.6 No.3
This study presents a novel Ant Colony Optimization (ACO) framework to solve a dynamic traveling sales-man problem. To maintain diversity via transferring knowledge to the pheromone trails from previous environments, Adaptive Large Neighborhood Search (ALNS) based immigrant schemes have been devel-oped and compared with existing ACO-based immigrant schemes available in the literature. Numerical results indicate that the proposed immigrant schemes can handle dynamic environments efficiently com-pared to other immigrant-based ACOs. Finally, a real life case study for wildlife surveillance (specifically, deer) by drones has been developed and solved using the proposed algorithm. Results indicate that the drone service capabilities can be significantly impacted when the dynamicity of deer are taken into consideration.
Evaluation of Low Power and High Speed CMOS Current Comparators
Rahman, Labonnah Farzana,Reaz, Mamun Bin Ibne,Marufuzzaman, Mohammad,Mashur, Mujahidun Bin,Badal, Md. Torikul Islam The Korean Institute of Electrical and Electronic 2016 Transactions on Electrical and Electronic Material Vol.17 No.6
Over the past few decades, CMOS current comparators have been used in a wide range of applications, including analogue circuits, MVL (multiple-valued logic) circuits, and various electronic products. A current comparator is generally used in an ADC (analog-to-digital) converter of sensors and similar devices, and several techniques and approaches have been implemented to design the current comparator to improve performance. To this end, this paper presents a bibliographical survey of recently-published research on different current comparator topologies for low-power and high-speed applications. Moreover, several aspects of the CMOS current comparator are discussed regarding the design implementation, parameters, and performance comparison in terms of the power dissipation and operational speed. This review will serve as a comparative study and reference for researchers working on CMOS current comparators in low-power and high-speed applications.
Evaluation of Low Power and High Speed CMOS Current Comparators
Labonnah Farzana Rahman,Mamun Bin Ibne Reaz,Mohammad Marufuzzaman,Mujahidun Bin Mashur,Md. Torikul Islam Badal 한국전기전자재료학회 2016 Transactions on Electrical and Electronic Material Vol.17 No.6
Over the past few decades, CMOS current comparators have been used in a wide range of applications, includinganalogue circuits, MVL (multiple-valued logic) circuits, and various electronic products. A current comparator isgenerally used in an ADC (analog-to-digital) converter of sensors and similar devices, and several techniques andapproaches have been implemented to design the current comparator to improve performance. To this end, thispaper presents a bibliographical survey of recently-published research on different current comparator topologiesfor low-power and high-speed applications. Moreover, several aspects of the CMOS current comparator are discussedregarding the design implementation, parameters, and performance comparison in terms of the power dissipationand operational speed. This review will serve as a comparative study and reference for researchers working on CMOScurrent comparators in low-power and high-speed applications.
Last mile delivery drone selection and evaluation using the interval-valued inferential fuzzy TOPSIS
Farjana Nur,Ayat Alrahahleh,Reuben Burch,Kari Babski-Reeves,Mohammad Marufuzzaman 한국CDE학회 2020 Journal of computational design and engineering Vol.7 No.4
The last mile delivery option has become a focal point of academic research and industrial development in recent years. Multiple factors such as increased demands on delivery flexibility, customer requirements, delivery urgency, and many others are enforcing to adopt this option. For fulfilling this paradigm shift in delivery and providing additional flexibility, drones can be considered as a viable option to use for last mile delivery cases. Numerous drones are available in the market with varying capacities and functionalities, posing a significant challenge for decision-makers to select the most appropriate drone type for a specific application. In this purpose, this study proposes a comprehensive list of criterions that can be used to compare a set of available last mile delivery drones. Additionally, we introduced a systematic multi-criterion, multi-personnel decision making approach, referred to as interval-valued inferential fuzzy TOPSIS method. This method is robust and can handle the fuzziness in decision making, thereby providing quality drone selection decisions under different applications. We then apply this method to a real-life test setting. Results suggest that smaller drones or quadcopters are considered viable to use in urban environments while long-range drones are preferred for the last mile delivery needs in rural settings.
High Performance CMOS Charge Pumps for Phase-locked Loop
Rahman, Labonnah Farzana,Ariffin, NurHazliza Bt,Reaz, Mamun Bin Ibne,Marufuzzaman, Mohammad The Korean Institute of Electrical and Electronic 2015 Transactions on Electrical and Electronic Material Vol.16 No.5
Phase-locked-loops (PLL) have been employed in high-speed data transmission systems like wireless transceivers, disk read/write channels and high-speed interfaces. The majority of the researchers use a charge pump (CP) to obtain high performance from PLLs. This paper presents a review of various CMOS CP schemes that have been implemented for PLLs and the relationship between the CP parameters with PLL performance. The CP architecture is evaluated by its current matching, charge sharing, voltage output range, linearity and power consumption characteristics. This review shows that the CP has significant impact on the quality performance of CP PLLs.
High Performance CMOS Charge Pumps for Phaselocked Loop
Labonnah Farzana Rahman,NurHazliza Bt Ariffin,Mamun Bin Ibne Reaz,Mohammad Marufuzzaman 한국전기전자재료학회 2015 Transactions on Electrical and Electronic Material Vol.16 No.5
Phase-locked-loops (PLL) have been employed in high-speed data transmission systems like wireless transceivers, disk read/write channels and high-speed interfaces. The majority of the researchers use a charge pump (CP) to obtain high performance from PLLs. This paper presents a review of various CMOS CP schemes that have been implemented for PLLs and the relationship between the CP parameters with PLL performance. The CP architecture is evaluated by its current matching, charge sharing, voltage output range, linearity and power consumption characteristics. This review shows that the CP has significant impact on the quality performance of CP PLLs.