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HIGH PERFORMANCE LOW Vcc DRAM`S WITH THE IVC USING Vcc DETECTING SCHEME
Yoo,Seung Moon,Yoo,Jei Hwan,Hwang,Hong Sun,Cho,Soo In,Lim,Hyung Kyu 대한전자공학회 1995 ICVC : International Conference on VLSI and CAD Vol.4 No.1
Low operating voltage in DRAM's is essential in meeting the demand for low power consumption in memories. This paper proposes an internal voltage converter(IVC) with Vcc detecting scheme to stabilize DRAM operation in the low Vcc region and thereby, extend the operating voltage margins. Operating voltage is detected at every RASB(Row Address Strobe Bar) falling edge and the IVC is controlled by the output of the Vcc detector. The voltage detector shows stable characteristics for temperature, fabrication process and reference voltage variations. 7% speedup(tRAC) and 0.2V extension in operating voltage margin for a 16M asynchronous DRAM and 50% and 0.5V for a 16M Synchronous DRAM are obtained.
Ki-Chul Chun,Jae-Yoon Sim,Hongil Yoon,Hyun-Seok Lee,Sang-Pyo Hong,Kyu-Chan Lee,Jei-Hwan Yoo,Dong-Il Seo 한국물리학회 2004 Current Applied Physics Vol.4 No.1
A 1.8 V low-voltage and low-power 128 Mb mobile SDRAM is designed and fabricated for hand-held, battery-operated elec-tronic devices with a 0.15-l m CMOS technology. As an essential low-voltage circuit, a triple pumping scheme is proposed togenerate a stable boosted voltage whose level exceeds over twice the supply voltage and which is required for the boosted word-linebias. In addition, to convert the bit-line data to a low-voltage CMOS level, a new NMOS and PMOS hybrid folded current senseamplier with dual-path current sensing scheme is proposed to obtain the stableI-to-V gain as well as to improve the low-voltage margin.