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A 2㎓ DLL-Based Frequency Multiplier for Dynamic Frequency Scaling
Jabeom Koo,Chulwoo Kim 대한전자공학회 2008 ICEIC:International Conference on Electronics, Inf Vol.1 No.1
A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a CMOS technology. The proposed clock generator can generate clock signals ranging from 125㎒ to 2㎓ and change the frequency dynamically in a short time. In addition, it can operate at a wide range operation frequency by using the proposed anti-harmonic lock block. The proposed DLL-based clock generator occupies 0.019㎟.
건물에너지시스템의 디지털 트윈을 위한 실물센서와 가상센서의 지속적인 동시보정 방법
구자범(JaBeom Koo),윤성민(SungMin Yoon) 대한설비공학회 2022 대한설비공학회 학술발표대회논문집 Vol.2022 No.11
최근 건물에너지시스템에서 다양한 지능형 기술들은 머신러닝 등을 통한 데이터 기반 접근법을 통해 개발되고 있다. 이에 건물에너지시스템에서 센서의 측정값에 대한 의존도가 점점 높아지고 있으며, 센싱환경에 대한 안정성과 신뢰성은 더욱 중요해졌다. 이러한 상황에서 더 정보적이고 신뢰할 수 있는 건물 센싱환경을 제공하기 위해 가상센싱 기술은 도입되었다. 하지만, 건물 운영에서 실물센서와 가상센서는 시스템 내 다양한 불확실한 요인들로 인하여 동시 다발적인 오류가 지속적으로 발생될 수 있다. 이에 장기적인 건물 운영에서 효과적인 사이버(cyber)-물리적 센싱환경을 구축하기 위한 현장보정 기술이 요구되는 실정이다. 본 연구에서는 베이지안 파라미터 추정 기법을 활용하여 건물에너지시스템에서 실물센서와 가상센서에 대한 지속적인 동시 현장 보정 방법을 제안한다. 실물센서와 가상센서의 동시적 보정을 위한 거리함수(distance function) 공식화와 장기적인 건물 운영에서 지속적인 현장 보정 기술의 성능을 제공하기 위해 2가지 전략을 제안하였다.
Sewook Hwang,Jabeom Koo,Kisoo Kim,Hokyu Lee,Chulwoo Kim IEEE 2013 IEEE transactions on circuits and systems. a publi Vol.60 No.9
<P>This paper presents a temperature sensor based on a frequency-to-digital converter with digitally controlled process compensation. The proposed temperature sensor utilizes ring oscillators to generate a temperature dependent frequency. The adjusted linear frequency difference slope is used to improve the linearity of the temperature sensor and to compensate for process variations. Furthermore, an additional process compensation scheme is proposed to enhance the accuracy under one point calibration. With one point calibration, the resolution of the temperature sensor is 0.18 <SUP>°</SUP>C/LSB and the maximum inaccuracy of 20 measured samples is less than ±1.5<SUP>°</SUP>C over a temperature range of 0<SUP>°</SUP>C ~ 110<SUP>°</SUP>C. The entire block occupies 0.008 mm<SUP>2</SUP> in 65 nm CMOS and consumes 500 μW at a conversion rate of 469 kS/s.</P>
A 6-bit 1.25-GS/s 1.94pJ/step Flash ADC in 0.13-㎛ CMOS
Jinwoo Kim,Jabeom Koo,Tagjong Lee,Chulwoo Kim 대한전자공학회 2008 ICEIC:International Conference on Electronics, Inf Vol.1 No.1
A 6-bit 1.25-GS/s 1.94pJ/step flash ADC with a switching reference ladder is presented. The proposed switching reference ladder method reduces the total number of comparators to almost two-thirds of that required in a conventional 6-bit flash ADC. Advantages of the switching reference ladder method are low-power consumption and small area due to the reduced number of comparators. The proposed flash ADC is implemented in a 0.13-㎛ CMOS technology and occupies 0.7 ㎟. The maximum sampling speed is 1.25㎓. The simulated SNDR and SFDR of 34 and 42 ㏈ at 20㎒ input have been achieved. The total power consumption of the converter at 1.25㎓ is 110㎽ from a 1.2-V supply.
An Antiharmonic, Programmable, DLL-Based Frequency Multiplier for Dynamic Frequency Scaling
Sunghwa Ok,Kyunghoon Chung,Jabeom Koo,Chulwoo Kim IEEE 2010 IEEE transactions on very large scale integration Vol.18 No.7
<P>This paper describes a new delay-locked loop (DLL)-based frequency multiplier, which includes a lock controller and a phase detector to solve the false lock problem and overcome the limited locking range of conventional DLLs. By using the multiple clock phases of the DLL, the lock controller is able to indicate whether the delay time of the VCDL is within the correct locking range or not. A differentially controlled edge combiner is also proposed for the frequency multiplication. The antiharmonic DLL-based frequency multiplier, implemented in a 0.18-μ.m CMOS process, occupies an active area of 0.043 mm<SUP>2</SUP>, and dissipates 36.7 mW at 1.7 GHz. The measured root mean square jitter and peak-to-peak jitter for the multiplied output clock at 1.7 GHz are 2.64 and 16.8 ps, respectively.</P>