A 6-bit 1.25-GS/s 1.94pJ/step flash ADC with a switching reference ladder is presented. The proposed switching reference ladder method reduces the total number of comparators to almost two-thirds of that required in a conventional 6-bit flash ADC. Adv...
A 6-bit 1.25-GS/s 1.94pJ/step flash ADC with a switching reference ladder is presented. The proposed switching reference ladder method reduces the total number of comparators to almost two-thirds of that required in a conventional 6-bit flash ADC. Advantages of the switching reference ladder method are low-power consumption and small area due to the reduced number of comparators. The proposed flash ADC is implemented in a 0.13-㎛ CMOS technology and occupies 0.7 ㎟. The maximum sampling speed is 1.25㎓. The simulated SNDR and SFDR of 34 and 42 ㏈ at 20㎒ input have been achieved. The total power consumption of the converter at 1.25㎓ is 110㎽ from a 1.2-V supply.