Local Field Switching 방식의 MRAM 설계

이감영(Gamyoung Lee),이승연(Seungyeon Lee),이현주(Hyunjoo Lee),이승준(Seungjun Lee),신형순(Hyungsoon Shin) 대한전자공학회 2008 電子工學會論文誌-SD (Semiconductor and devices) Vol.45 No.8

본 논문에서는 새로운 스위칭 방식인 LFS (Local Field Switching)을 이용하여 설계한 128비트 MRAM (Magnetoresistive Random Access Memory)에 대해 기술하였다. LFS 방식은 MTJ (Magnetic Tunnel Junction)를 직접 통과해 흐르는 전류에 의해 형성되는 국소 자기장을 이용하여 MTJ의 극성을 변환시킨다. 이 방식은 MTJ와 전류의 거리가 가깝기 때문에 작은 전류로도 충분히 큰 자기장을 형성하므로 writing current가 적어도 된다. 또한 Digit Line이 없어도 되므로 half select disturbance가 발생하지 않아 기존 MTJ를 이용한 방식에 비해 셀 선택도가 우수하다. 설계한 MRAM은 1T(트랜지스터)-1MTJ의 메모리 셀 구조를 가지며 양방향 write driver와 mid-point reference cell block, current mode sense amplifier를 사용한다. 그리고 MTJ 공정 없이 회로 동작을 확인하기 위해 LFS-MTJ cell을 CMOS emulation cell로 대체하였다. 설계한 회로를 6 metal을 사용하는 0.18㎛ CMOS 공정으로 구현하였고 제작된 chip을 custom board 상에서 테스트하여 동작을 확인하였다. In this paper, we describe a design of a 128bit MRAM based on a new switching architecture which is Local Field Switching(LFS). LFS uses a local magnetic field generated by the current flowing through an MTJ. This mode reduces the writing current since small current can induce large magnetic field because of close distance between MTJ and the current. It also improves the cell selectivity over using conventional MTJ architecture because it doesn't need a digit line for writing. The MRAM has 1-Transistor 1-Magnetic Tunnel Junction (1T-1MTJ) memory cell structure and uses a bidirectional write driver, a mid-point reference cell block and a current mode sense amplifier. CMOS emulation cell is adopted as an LFS-MTJ cell to verify the operation of the circuit without the MTJ process. The memory circuit is fabricated using a 0.18 ㎛ CMOS technology with six layers of metal and tested on custom board.

Magneto-Logic Device Based on a Single-Layer Magnetic Tunnel Junction

Lee, Seungyeon,Choa, Sunghoon,Lee, Seungjun,Shin, Hyungsoon Institute of Electrical and Electronics Engineers 2007 IEEE transactions on electron devices Vol.54 No.8

<P> A magnetic tunnel junction (MTJ) element can compute Boolean functions and also store the output of its last operation. Therefore, the MTJ shows potential for a universal logic element to implement sequential-logic functions as well as combinatorial ones. The established magneto-logic element has been designed and fabricated based on a triple-layer MTJ. We present a novel magneto-logic structure that consists of a single-layer MTJ and a current driver, which requires less processing steps with enhanced functional flexibility and uniformity. </P>

Analysis of stress field in a single anisotropic diamond/square shaped inclusion using the volume integral equation method and the numerical equivalent inclusion method

Lee, Jungki,Nozaki, Hideaki,Lee, Hyungsoon Informa UK (TaylorFrancis) 2018 COMPOSITE INTERFACES -ZEIST- Vol.25 No.3

The 3-Bit Gray Counter Based on Magnetic-Tunnel-Junction Elements

Seungyeon Lee,Nakmyeong Kim,Heejung Yang,Gamyoung Lee,Seungjun Lee,Hyungsoon Shin IEEE 2007 IEEE transactions on magnetics Vol.43 No.6

<P>A magnetic-tunnel-junction (MTJ) element has been widely studied for data storage applications. An MTJ element can also be used to compute Boolean functions and store the output result. A magnetologic device based on this MTJ element can constitute sequential logic functions as well as combinational logic. Counter is one of the most frequently used sequential logic blocks in digital logic systems. In this paper, a novel architecture of a 3-bit gray counter based on magnetologic elements is presented. It is shown that ten MTJ elements with complementary metal-oxide-semiconductor (CMOS) circuits for sense amplifier and writing-current driver can make a 3-bit gray counter. HSPICE simulation results are presented to verify the functionality of the proposed circuits</P>

조달입찰(Procurement Auction)의 성과개선을 위한 프로세스 및 경쟁 최적화 모델 설계

이형순 ( Hyungsoon Lee ),김창은 ( Changeun Kim ) 한국경영공학회 2021 한국경영공학회지 Vol.26 No.1

Purpose This study is about to establish standards for process design and operation of procurement auction, which is one of the ways to effectively determine the price with the vendor in the procurement. Methods The method of research was selected as a case company in which various forms of procurement are carried out. In the process design of procurement auction, We derived from RCA method how to improve the constraints for evaluating multiple attributes. In order to establish the operating standards for procurement auction, 720 cases of approximately 3.5 years were tested through statistical analysis and based on this, the operating standards for procurement auctions were proposed. Results This study shows, The design of the procurement auction using Fishbone Diagram was able to expand the bid by mitigating the avoidance factor of multi-attribute evaluation, and the results of completion inspection can be analyzed to confirm its. Procurement auction is an advantageous method of price determination compared to negotiated pricing in cases where the order amount is large and it is difficult for the person in charge to calculate the expected price. An analysis of the winning price of new companies showed that new companies are challengingly offering prices and that such competitiveness continues for two to three years. In addition, it was analyzed that the bid reaches a stable and reliable bid price when there are more than four bidders participants. Conclusion The results illustrate, this study proposed a multi-attribute assessment process design method for procurement auction and defined criteria that could be effective in bidding operation, such as number of participants, sourcing new companies, and improving expected price estimation capability.

단층 입력 구조의 Magnetic-Tunnel-Junction 소자를 이용한 임의의 3비트 논리회로 구현을 위한 자기논리 회로 설계

이현주(Hyunjoo Lee),김소정(Sojeong Kim),이승연(Seungyeon Lee),이승준(Seungjun Lee),신형순(Hyungsoon Shin) 대한전자공학회 2008 電子工學會論文誌-SD (Semiconductor and devices) Vol.45 No.12

Magnetic Tunnel Junction (MTJ) 는 비휘발성 소자로서 그간 기억소자분야에 국한되어왔으나, 최근 다양한 연구들에 의하여 자기논리 (magneto-logic) 회로에 사용되면서 기존 트랜지스터 기반의 논리연산자를 대체할 수 있는 가능성을 보이고 있으며, 논리회로까지 확장 적용되어 스핀전자공학 분야의 새로운 장을 열 것으로 기대되어지고 있다. 자체 저장 능력을 갖는 MTJ 소자로 구현된 자기논리 회로는 전원이 꺼져도 정보가 그대로 유지되고, 또한, 불 (Boolean) 연산 수행 시 단순한 입력변화만으로 다양한 논리 연산자 구현이 가능한 구조적인 유연성을 보이므로, 물리적으로 완성된 회로 내에서 얼마든지 재구성이 가능한 자기논리 회로를 구현할 수 있다. 본 논문에서는 단순한 조합논리나 순차논리 회로의 동작을 넘어서, 임의의 3비트 논리회로 동작을 모두 수행할 수 있는 자기논리 회로를 제안한다. 이를 위해 3비트 논리회로 중에서 최대의 복잡성을 갖는 논리회로를 MTJ 소자를 사용하여 설계하였고, 그 동작을 이전 논문에서 제안된 바 있는 macro-model을 보완 적용하여 검증하였다. 제안된 회로는 3비트로 구현할 수 있는 가장 복잡한 논리회로의 동작을 수행할 뿐만 아니라, 전류구동회로의 게이트 신호들을 변화시킴으로써 임의의 3비트 논리회로의 동작을 모두 수행하는 것이 가능하다. Magnetic Tunneling Junction (MTJ) has been used as a nonvolatile universal storage element mainly in memory technology. However, according to several recent studies, magneto-logic using MTJ elements show much potential in substitution for the transistor-based logic device. Magneto-logic based on MTJ can maintain the data during the power-off mode, since an MTJ element can store the result data in itself. Moreover, just by changing input signals, the full logic functions can be realized. Because of its programmability, it can embody the reconfigurable magneto-logic circuit in the rigid physical architecture. In this paper, we propose a novel 3-bit arbitrary magneto-logic circuit beyond the simple combinational logic or the short sequential one. We design the 3-bit magneto-logic which has the most complexity using MTJ elements and verify its functionality. The simulation results are presented with the HSPICE macro-model of MTJ that we have developed in our previous work. This novel magneto-logic based on MTJ can realize the most complex logic function. What is more, 3-bit arbitrary logic operations can be implemented by changing gate signals of the current driver circuit.

Evanescent-Mode Analysis of Short-Channel Effects in MOSFETs

Jiyeong Lee,Hyungsoon Shin 한국물리학회 2004 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.44 No.1

The short channel effects (SCE) of bulk MOSFETs with super-steep retrograded channels (SSR), fully-depleted SOI, and double-gate MOSFETs have been analyzed using device simulations and a scaling-length () analysis. It is found that the minimum channel length should be larger than 5 and that the depletion thickness of the SSR should be around 30 nm in order to be applicable to 70-nm CMOS technology. A high-kappa dielectric shows a limitation in scaling due to the drain- field penetration through the dielectric unless the equivalent SiO2 thickness is very thin. The SSR gives the smallest SCE of the three structures considered.

Self‐Assembled Plasmonic Nanoring Cavity Arrays for SERS and LSPR Biosensing

Im, Hyungsoon,Bantz, Kyle C.,Lee, Si Hoon,Johnson, Timothy W.,Haynes, Christy L.,Oh, Sang‐,Hyun WILEY‐VCH Verlag 2013 ADVANCED MATERIALS Vol.25 No.19

<P><B>Self‐assembled plasmonic nanoring cavity arrays</B> are formed alongside the curvature of highly packed metallic nanosphere gratings. The sub‐10‐nm gap size is precisely tuned via atomic layer deposition and highly ordered arrays are produced over a cm‐sized area. The resulting hybrid nanostructure boosts coupling efficiency of light into plasmons, and shows an improved SERS detection limit. These substrates are used for SERS detection of the biological analyte, adenine, followed by concurrent localized surface plasmon resonance sensing.</P>

Switching Time and Stability Evaluation for Writing Operation of STT-MRAM Crossbar Array

Lim, Hyein,Lee, Seungjun,Shin, Hyungsoon Institute of Electrical and Electronics Engineers 2016 IEEE transactions on electron devices Vol.63 No.10

<P>The dynamic characteristics of a spin transfer torque magnetoresistive random access memory crossbar array during write operations were investigated. A spin transfer torque magnetic tunnel junction was combined with a two-terminal selector device instead of a three-terminal CMOS transistor in the crossbar array architecture. The characteristics of the crossbar array architecture were investigated under different bias schemes and transient simulations of write operations were performed under various operating conditions. The variance of the switching time and problematic behaviors was investigated. The floating bias scheme was compared with the 1/2 bias scheme, and simulation results revealed that write errors may be induced in the floating bias scheme by abnormal glitches occurring when the parasitic capacitance becomes large.</P>

The Clinical Feasibility of Inferior Right Hepatic Vein-preserving Right Hepatecotmy

Sunghoon Choi,Hyungsoon Lee,Jinhong Lim,Gihong Choi,Jinsub Choi 한국간담췌외과학회 2012 한국간담췌외과학회 학술대회지 Vol.2012 No.4