Redeposition mechanism on silicon oxide layers during selective etching process in 3D NAND manufacture

Zihan Zhou,Yunwen Wu,Huiqin Ling,Jie Guo,Su Wang,Ming Li 한국공업화학회 2023 Journal of Industrial and Engineering Chemistry Vol.119 No.-

3D NAND flash memory with vertically stacked cells has been developed to break through the limits oftechnology nodes. However, during the selective etching process, it is difficult to ensure the byproductsdiffuse away from the trenches in the multistacked layers. Once saturated, the byproduct causes abnormalredeposition on the SiO2 layers. This problem has restricted the development of high-density 3DNAND memory. To solve this problem, the composition and formation mechanism of the redepositedlayer must be clarified. In this study, a ternary-wafer system comprising a Si3N4/SiO2/Si3N4 stack was fabricatedto study the redeposition mechanism, and the morphology, elastic properties, and chemical compositionof the redeposited layer were clarified. The redeposited layer consists of spherical particles withelastic surfaces (average Young’s modulus of 24.17 GPa). The particles were confirmed to comprise colloidalsilica gel covered by silanols. By considering the chemistry of silica, the redeposition mechanismwas proposed as follows: colloidal silica gel is formed by the aggregation of silicic acids from Si3N4 etching,which adsorb onto the SiO2 layer through oxide bridges and hydrogen bonding. Our work will contributeto the development of high-density 3D NAND memory.

Liner sweep voltammetry electroplating method to synthesize large monocrystalline Cu cones for interconnection

Hua Hu,Ruoxun Zhang,Yunwen Wu,Huiqin Ling,Tao Hang,Ming Li 대한금속·재료학회 2022 ELECTRONIC MATERIALS LETTERS Vol.18 No.1

As the size of interconnect technology in integrated circuits keeps minimizing, the electrical resistivity and signal transmission delay become increasingly serious. The monocrystalline materials can meet the requirements of miniaturization and high-speed interconnection, which is a proper solution of these problems. Hence, we fabricated large monocrystalline Cu cones with (111) orientation using a linear sweep voltammetry electroplating method for the first time. It was found that phosphorus could induce texturization of polycrystals at a certain potential. The grains with uniform orientation grown into single crystals through the oriented attachment growth mechanism. The screw dislocations produced during oriented attachment led to crystal spiral growth, developing into large monocrystalline cones. This work is expected for application in copper interconnect technology in the future.

The evolution of microstructure and resistance in electroplated copper films by linear integrated laser scanning annealing

Lingyue Tan,Silin Han,Shuhui Chen,Tao Hang,Huiqin Ling,Yunwen Wu,Ming Li 대한금속·재료학회 2021 ELECTRONIC MATERIALS LETTERS Vol.17 No.2

Thermal treatment is an effective way to decrease the resistivity and internal stress by inducing grain growth accompaniedwith redistribution of embedded impurities. With the narrowing of Cu interconnects in IC packaging, the increased resistanceis becoming the main issue that hindering the electrical performance of IC. Herein, a laser annealing method by linerscanning (LALS) to anneal the Cu interconnects were reported which provide a gradient thermal field for the crystallographic/microstructure transition. The impacts of laser annealing on the sheet resistance of the electroplating Cu films wereinvestigated in aspects of microstructure and phase field simulation. Cu films treated by LALS owned larger average grainsize, better recrystallization fraction, and significantly higher average grain aspect ratio than conventional annealing, whichindicated the increased driving force for grain boundaries evolution by LALS method. This study exhibited the direct evidenceon the impacts of laser annealing process on the resistance of electroplated Cu films. The laser annealing process witha local temperature gradient caused a significant decline in Cu electrical resistance compared to the conventional annealingprocess, indicating its extraordinary potential in improving Cu wire conductivity. This work will provide a scientific basis forselecting the post-treatment process for electrodeposited Cu films to achieve ideal electrical properties and microstructurein electronics industry applications.

Sub-surface Damage of Ultra-Thin Monocrystalline Silicon Wafer Induced by Dry Polishing

Xundi Zhang,Chenlin Yang,Yumei Zhang,Anmin Hu,Ming Li,Liming Gao,Huiqin Ling,Tao Hang 대한금속·재료학회 2020 ELECTRONIC MATERIALS LETTERS Vol.16 No.4

Ultra-thin wafer fabrication has become a hot spot in recent years with the growing demand for small size and high performance electronic devices. However, far less research focused on the damage behavior in ultra-thin wafer. In this work, 300 mm diameter silicon wafer was thinned to 6 µm thick by grinding plus ultra-precision dry polishing. The damage behavior before and after the dry polishing was discussed. Mechanical and surface analysis showed that the dry polishing process can help improve the strength and surface uniformity of ultra-thin wafer by removing high pressure phase and micro cracks. Series of nano beam diffraction patterns revealed the stress induced by the thinning process only existed in surface. High resolution transmission electron microscopy images analyzed by geometric phase approach indicated that surface dislocations can move across the wafer and reached bottom device layers during the dry polishing, increasing the risk of electrical deterioration. The findings are of great significance to the study on process optimization of ultra-thin wafer and provide insights into the reliability of advanced electronic packaging.

Effects of Sn Layer Orientation on the Evolution of Cu/Sn Interfaces

Menglong Sun,Zhangjian Zhao,Fengtian Hu,Anmin Hu,Ming Li,Huiqin Ling,Tao Hang 대한금속·재료학회 2018 ELECTRONIC MATERIALS LETTERS Vol.14 No.4

The effects of Sn layer orientation on the evolution of Cu/Sn joint interfaces were investigated. Three Sn layers possessing(112), (321) and (420) orientations were electroplated on polycrystalline Cu substrates respectively. The orientations of Snlayer preserved during reflowing at 250 °C for 10 s. After aging at 150 °C for different time, the interfacial microstructureswere observed from the cross-section and top-view. The alignment between the c-axis of Sn and Cu diffusion direction significantlysped up the Cu diffusion, leading to the thickest intermetallic compound layer formed in (112) joint. Two types ofvoids, namely, intracrystalline voids and grain islanding caused intercrystalline voids generated at Cu/Cu3Sn interfaces dueto the different interdiffusion coefficients of Cu and Sn (112) oriented Sn/Cu joint produced many more voids than (321)joint, and no voids were detected in (420) joint. Therefore, to enhance the reliability of solder joints, using (420) orientedSn as solder layer could be an efficient way.

Formation Mechanism of Novel Sidewall Intermetallic Compounds in Micron Level Sn/Ni/Cu Bumps

Siru Ren,Menglong Sun,Zebin Jin,Yukun Guo,Huiqin Ling,Anmin Hu,Ming Li 대한금속·재료학회 2019 ELECTRONIC MATERIALS LETTERS Vol.15 No.5

A new kind of intermetallic compounds (IMC) were found around copper pillar in micron level bumps. To investigate theformation mechanism, three different sized Sn/Ni/Cu bumps (10 μm, 20 μm, 50 μm) were electroplated then reflowed at230 °C for 100 s. After reflow process, a thin layer of IMC was formed around copper pillar, which is attributed to surfacewetting behavior. After aging at 170 °C and 200 °C for different times, the growth mechanism of sidewall IMC was observedby scanning electron microscopy combined with electron backscatter diffraction (EBSD) technology. Surface diffusion wasconsidered to be the main driving force for sidewall IMC growth for the activation energy of them was found to be muchsmaller than that in previous studies. The EBSD results showed a preferred orientation of sidewall Cu3Sngrains <100> beingperpendicular to copper periphery, which indicated direction of Cu atoms flux during Cu3Sngrowth. Formation mechanismof this novel sidewall IMC was proposed based on surface wetting and surface diffusion. The findings contribute to the failuremechanism study in small size bumps and provide insights into the reliability of 3D electronic packaging.

Low-temperature insertion bonding using electroless Cu-Co-P micro-cones array with controllable morphology

Yaqian Sun,Jing Wang,Xundi Zhang,Chenlin Yang,Anmin Hu,Tao Hang,Yunwen Wu,Huiqin Ling,Ming Li 대한금속·재료학회 2021 ELECTRONIC MATERIALS LETTERS Vol.17 No.6

At present, thermal compression bonding based on Cu and lead-free Sn based solder is often limited by high bonding temperature,which is higher than the melting point of solder (218 ℃). In this paper, we reported a low-temperature solid stateinsertion bonding method based on electroless Cu-Co-P micro-cones array. By adjusting the mass ratio of CuSO 4 ·5H 2 O andCoSO 4 ·7H 2 O, a series of Cu-Co-P micro-cones with diff erent morphologies were prepared. The Cu-Co-P micro-cones withhigher proportion of copper were sharper and denser and (111) orientation was also more. It was found that reducing theheight and density of micro-cones was conducive to achieve seamless bonding at lower temperature and force such as 170℃ and 750 gf. By optimizing the morphology of micro-cones, such as height, bottom diameter, vertex angle and density, theseamless and reliable bonding with high shear strength (39.9 MPa) could be achieved at 170 ℃ bonding temperature and1000 gf bonding force. The transmission electron microscopy results showed that intermetallic compounds including Cu 6 Sn 5and Cu 3 Sn existed at bonding interface, which indicated that signifi cant atomic diff usion had occurred between Cu-Co-Pmicro-cones and Sn based solder. Probable mechanisms for low-temperature insertion bonding were discussed.