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An FPGA-based Parallel Hardware Architecture for Real-time Eye Detection
Dongkyun Kim,Junhee Jung,Thuy Tuong Nguyen,Daijin Kim,Munsang Kim,Key Ho Kwon,Jae Wook Jeon 대한전자공학회 2012 Journal of semiconductor technology and science Vol.12 No.2
Eye detection is widely used in applications, such as face recognition, driver behavior analysis, and human-computer interaction. However, it is difficult to achieve real-time performance with software-based eye detection in an embedded environment. In this paper, we propose a parallel hardware architecture for real-time eye detection. We use the AdaBoost algorithm with modified census transform(MCT) to detect eyes on a face image. We parallelize part of the algorithm to speed up processing. Several downscaled pyramid images of the eye candidate region are generated in parallel using the input face image. We can detect the left and the right eye simultaneously using these downscaled images. The sequential data processing bottleneck caused by repetitive operation is removed by employing a pipelined parallel architecture. The proposed architecture is designed using Verilog HDL and implemented on a Virtex-5 FPGA for prototyping and evaluation. The proposed system can detect eyes within 0.15 ㎳ in a VGA image.
개방형 가상스위치 기반의 패킷가속화기술을 이용한 네트워크 성능 측정 및 분석
김기현 ( Ki-hyeon Kim ),김용환 ( Yong-hwan Kim ),김주범 ( Joobum Kim ),김동균 ( Dongkyun Kim ) 한국정보처리학회 2017 한국정보처리학회 학술대회논문집 Vol.24 No.1
제 4차 산업혁명의 등장으로 다양한 기술들이 주목받고 있으며, 이 중에서 가장 주목 받고 있는 기술은 빅 데이터 기술이다. 이에 따라 최근 빅 데이터를 이용하기 위한 기업들이 크게 증가하고 있고, 해당 기업들을 위해서 방대한 데이터를 빠르게 전송 및 처리할 수 있는 고성능 네트워킹의 필요성이 증가하고 있다. 데이터의 전송과 처리 속도를 향상시키는 직접적인 방안으로 물리적인 네트워크 장비를 증설할 수 있지만 이는 상당한 비용의 증가를 초래하므로, 이를 해결하기 위해 네트워크 가상화 기술이 대두되었다. 하지만 네트워크 가상화 기술은 네트워크의 성능을 보장할 수 없다는 문제점을 가진다. 이러한 문제가 발생하는 주된 이유는 서버의 운영체제 커널 단에서 패킷을 처리하는 과정에서 성능을 저하시키는 요소들이 다수 존재하기 때문이며, 이를 해결하기 위해 나타난 기술이 패킷가속화기술이다. 본 논문에서는 개방형가상스위치 기반의 패킷가속화기술을 적용한 실험환경을 구성한 후, 이를 통해 가상 스위치 기반의 성능 시험과 패킷가속화기술을 이용한 서비스 체이닝 기술에 대한 성능 시험을 수행했다. 그리고 두 가지 시험을 통해 패킷가속화기술의 안정성과 성능을 검증하였다.
A river environment index for Korean national rivers: rationale, methods and application
Kim, Dongkyun,Park, Tae-Sun,Park, Jeryang,Lee, Seung-Oh IWA Publishing 2014 Water policy Vol.16 No.3
<P>A methodology for indexing river environmental condition was developed and applied to 269 subsections of national rivers located in the Republic of Korea, based on a river management perspective. The resulting index has been called the River Environment Index (REI). To develop the methodology, a total of 32 factors related to a river's environment were initially investigated, from which 16 were chosen based on their measurability, predictability, measurement regularity and obtainability. Then, using the analytical hierarchy process (AHP) and based on a survey of 62 river management experts in Korea, the weighting coefficient for each of the 16 factors was determined. Finally, the REI values were estimated by linearly combining the 16 measured factors for the 269 river subsections and mapped using a geospatial information system platform. We expect that the REI will be used to increase the efficient allocation of national budgets for environmentally-friendly river restoration projects of the country's national rivers. Through this new index, prioritization of these rivers will be made using an holistic river management perspective.</P>
Kim, YongJo,Song, Keunsoo,Kim, Dongkyun,Cho, SeongHwan IEEE 2017 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.64 No.4
<P>In this brief, we propose a quadrature signal corrector for a low-power DDR4 mobile DRAM interface. In order to eliminate the phase imbalance among quadrature signals, the proposed architecture employs digitally controlled delay lines in a shared digital feedback loop with a time-multiplexed loop filter so as to minimize the effect of circuit mismatch that hampers the phase accuracy. A self-calibrated offset delay is also proposed, which allows the use of a simple 1-bit TDC instead of a power-hungry wide-dynamic range TDC. Implemented in 65-nm CMOS, the prototype chip achieves less than 1.1-ps phase error for a 1.25-GHz quadrature signal and occupies an active area of only 0.01 mm(2) while consuming 2.27 mW from a 1.0-V supply.</P>