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핵활동 모니터링을 위한 소형객체 비율에 따른 U-Net의 의미론적 분할 성능 비교
이진민,김태헌,이창희,이현진,송아람,한유경,Lee, Jinmin,Kim, Taeheon,Lee, Changhui,Lee, Hyunjin,Song, Ahram,Han, Youkyung 대한원격탐사학회 2022 大韓遠隔探査學會誌 Vol.38 No.6
원격탐사 기술을 활용한 접근불능 지역에 대한 핵활동 모니터링은 핵 비확산을 위해 필수적이다. 최근에는 딥러닝을 이용하여 핵활동 관련 객체를 탐지하는 연구가 활발하게 수행되고 있으나, 고해상도 위성영상 내 소형객체는 클래스 불균형 발생 빈도가 높다. 이로 인해 소형객체 탐지 성능이 저하되는 문제점이 존재한다. 이에 본 연구에서는 입력 데이터 내 핵활동 관련 소형객체의 비율이 딥러닝 모델 성능에 미치는 영향을 분석하여 탐지 정확도를 개선하기 위한 방안을 도출하고자 한다. 이를 위해 소형객체 비율이 상이한 6가지 학습자료를 구축하여 학습자료별로 U-Net 모델 학습을 진행하고, 다양한 종류의 소형객체가 포함된 test dataset을 이용하여 학습된 U-Net 모델 간 정량적·정성적 비교평가를 수행하였다. 그 결과, 입력영상 내 객체 픽셀 비율을 조절하였을 때 핵활동 관련 소형객체를 효과적으로 탐지할 수 있는 것이 확인되었으며, 이를 통해 훈련 자료 내 객체 비율을 조정하여 딥러닝 모델 성능을 향상시킬 수 있을 것으로 판단된다.
누설전류 감소를 위한 Bird's Beak 공정을 이용한 다결정 실리콘 박막 트랜지스터의 구조 연구
이진민,Lee, Jin-Min 한국전기전자재료학회 2011 전기전자재료학회논문지 Vol.24 No.2
To stabilize the electric characteristic of Silicon Thin Film Transistor, reducing the current leakage is most important issue. To reduce the current leakage, many ideas were suggested. But the increase of mask layer also increased the cost. On this research Bird's Beak process was use to present element. Using Silvaco simulator, it was proven that it was able to reduce current leakage without mask layer. As a result, it was possible to suggest the structure that can reduce the current leakage to 1.39nA without having mask layer increase. Also, I was able to lead the result that electric characteristic (on/off current ratio) was improved compare from conventional structure.
실리콘 게이트전극을 갖는 고온소자와 금속 게이트전극을 갖는 P형 저온 다결정 실리콘 박막 트랜지스터의 전기특성 비교 연구
이진민,Lee, Jin-Min 한국전기전자재료학회 2011 전기전자재료학회논문지 Vol.24 No.6
Poly Si TFTs (poly silicon thin film transistors) with p channel those are annealed HT (high temperature) with gate poly crystalline silicon and LT (low temperature) with metal gate electrode were fabricated on quartz substrate using the analyzed data and compared according to the activated grade silicon thin films and the size of device channel. The electrical characteristics of HT poly-Si TFTs increased those are the on current, electron mobility and decrease threshold voltage by the quality of particles of active thin films annealed at high temperature. But the on/off current ratio reduced by increase of the off current depend on the hot carrier applied to high gate voltage. Even though the size of the particles annealed at low temperature are bigger than HT poly-Si TFTs due to defect in the activated grade poly crystal silicon and the grain boundary, the characteristics of LT poly-Si TFTs were investigated deterioration phenomena those are decrease the electric off current, electron mobility and increase threshold voltage. The results of transconductance show that slope depend on the quality of particles and the amplitude depend on the size of the active silicon particles.
스텝 어닐링에 의한 저온 및 고온 n형 다결정 실리콘 박막 트랜지스터의 전기적 특성 분석
이진민,Lee, Jin-Min 한국전기전자재료학회 2011 전기전자재료학회논문지 Vol.24 No.7
In this paper, experimental analyses have been performed to compare the electrical characteristics of n channel LT(low temperature) and HT(high temperature) poly-Si TFTs(polycrystalline silicon thin film transistors) on quartz substrate according to activated step annealing. The size of the particles step annealed at low temperature are bigger than high temperature poly-Si TFTs and measurements show that the electric characteristics those are transconductance, threshold voltage, electric effective mobility, on and off current of step annealed at LT poly-Si TFTs are high more than HT poly-Si TFT's. Especially we can estimated the defect in the activated grade poly crystalline silicon and the grain boundary of LT poly-Si TFT have more high than HT poly-Si TFT's due to high off electric current. Even though the size of particles of step annealed at low temperature, the electrical characteristics of LT poly-Si TFTs were investigated deterioration phenomena that is decrease on/off current ratio depend on high off current due to defects in active silicon layer.
고온에서 제작된 n채널 다결정 실리콘 박막 트랜지스터의 단채널 효과 연구
이진민,Lee, Jin-Min 한국전기전자재료학회 2011 전기전자재료학회논문지 Vol.24 No.5
To integrate the sensor driver and logic circuits, fabricating down scaled transistors has been main issue. At this research, short channel effects were analyzed after n channel polycrystalline silicon thin film transistor was fabricated at high temperature. As a result, on current, on/off current ratio and transconductance were increased but threshold voltage, electron mobility and s-slope were reduced with a decrease of channel length. When carriers that develop at grain boundary in activated polycrystalline silicon have no gate biased, on current was increased with punch through by drain current. Also, due to BJT effect (parallel bipolar effect) that developed under region of channel by increase of gate voltage on current was rapidly increased.
폴리이미드 박막과 스퍼터링 방법으로 증착한 상부금속 그레인이 용량형 습도센서의 전기적 특성에 미치는 영향
이진민,Lee, Jin-Min 한국전기전자재료학회 2011 전기전자재료학회논문지 Vol.24 No.3
This research, integratable capacitive relative humidity sensor was produced using polyimide on glass substrate. Also, at the time of upper electrode formation, upper electrode grain size was affected by giving changes to sputtering condition. Through this analyzing electrical characteristics affect from capacitive relative humidity sensor was possible. Capacitance of capacitive relative humidity sensor was 330 pF, linearity of 0.6%FS and it showed less than 3% of low hysterisis. Specially, hysterisis was affected more from interface than interstitial. Also was affected by the grain size which is one of the formation condition of upper electrode.
고온에서 제조된 실리콘 주입 p채널 다결정 실리콘 박막 트랜지스터의 전기 특성 변화 연구
이진민,Lee, Jin-Min 한국전기전자재료학회 2011 전기전자재료학회논문지 Vol.24 No.5
Analyzing electrical degradation of polycrystalline silicon transistor to applicable at several environment is very important issue. In this research, after fabricating p channel poly crystalline silicon TFT (thin film transistor) electrical characteristics were compare and analized that changed by gate bias with first measurement. As a result on and off current was reduced by variation of gate bias and especially re duce ratio of off current was reduced by $7.1{\times}10^1$. On/off current ratio, threshold voltage and electron mobility increased. Also, when channel length gets shorter on/off current ratio was increased more and thresh old voltage increased less. It was cause due to electron trap and de-trap to gate silicon oxide by variation of gate bias.
이진민(Jin Min Lee),유정훈(Jung Hoon Yoo),이민욱(Min Uk Lee),이태희(Tae Hee Lee) 대한기계학회 2004 대한기계학회 춘추학술대회 Vol.2004 No.10
Three methods for design sensitivity analysis such as finite difference method, direct differentiation method and adjoint variable method are well known. Finite difference method and direct differentiation method for design sensitivity analysis costs too much when number of design variables is too large. Therefore, an adjoint variable method is suggested for the case that the dimension of design variables is very large. An adjoint variable method is required to compute adjoint variables from the simultaneous linear system equation, the so-called adjoint equation. The adjoint equation is requiring only the eigenvalue and its corresponding eigenvector for the mode being differentiated. This method has been extended to the eigenproblem of damped systems. Moreover, this method is implemented into a commercial finite element analysis program to show applicability of the developed method into general structure problems. Two examples are illustrated to verify the developed method.
이진민(Jin Min Lee),이민욱(Min Uk Lee),조수길(Su Kil Cho),구만회(Man Hoi Koo),김학인(Hak In Gimm),이태희(Tae Hee Lee) 대한기계학회 2008 대한기계학회 춘추학술대회 Vol.2008 No.11
An open frame structure is fastened by bolt joints for strength and shock attenuation. Therefore the full finite element model of an open frame structure should be properly modeled including bolt joints for strength analysis of the frames and joint assemblies which are operated under multi-loading conditions such as driving, drop, inertia and torsional loads. Then the joints and frames must satisfy the specified allowable strength constraints. Because the full finite element model has a large number of elements to perform strength analysis, a detailed fine bolt analysis seems to be very expensive. Therefore bolts of the full finite element model are approximately modeled by constraints equations to constrain degree of freedoms between adjacent nodes. However, the constraints equation method can exaggerate stress results at the constrained nodes. Thus a detailed bolt analysis and a theoretical/experiential formula of bolts for a worst bolt joint are performed using reaction force applied both bolt and bolt joint. Finally, the results from the two methods are compared and discussed to verify the safety of the open frame structure.