결정질 실리콘 태양전지 응용을 위한 SiN_x 및 SiO₂ 박막의 패시베이션 특성 연구

정명일,최철종,Jeong, Myung-Il,Choi, Chel-Jong 한국결정성장학회 2014 한국결정성장학회지 Vol.24 No.1

다양한 공정 조건으로 $SiN_x$와 $SiO_2$ 박막을 형성하고 이에 대한 패시베이션 특성에 대한 연구를 수행하였다. Plasma enhanced chemical vapor deposition(PECVD)을 이용하여 증착된 $SiN_x$ 박막의 경우, 증착 두께가 증가함에 따라 페시베이션 특성이 향상되는 것을 관찰하였다. 이는 PECVD 증착 공정 중 유입되는 수소 원자들이 실리콘 표면에 존재하는 Dangling bond와 결합하여 소수 캐리어의 재결합 현상을 효과적으로 감소시켰기 때문이다. 건식 산화법으로 형성된 $SiO_2$ 박막은 습식 산화법으로 형성된 것 보다 치밀한 계면 구조를 가짐으로 인하여 약 20배 이상 우수한 패시베이션 특성을 나타내었다. 건식 산화 공정 온도가 증가함에 따라 패시베이션 특성이 열화되는 현상이 발생하였고, Capacitance-voltage(C-V) 및 Conductance-voltage(G-V) 분석을 통하여 $SiO_2$/실리콘 계면에 존재하는 계면 결함 밀도 증가에 의해 나타나는 현상임을 알 수 있었다. We have investigated the passivation property of $SiN_x$ and $SiO_2$ thin films formed using various process conditions for the application of crystalline Si solar cells. An increase in the thickness of $SiN_x$ deposited using plasma enhanced chemical vapor deposition (PECVD) led to the improvement of passivation quality. This could be associated with the passivation of Si dangling bonds by hydrogen atoms which were supplied during PECVD deposition. The $SiO_2$ thin films grown using dry oxidation process exhibited better passivation behavior than those using wet oxidation process, implying the dry oxidation process was more effective in the formation of high quality $SiO_2$ thin films. The relative effective life time gradually decreased with increasing dry oxidation temperature. Such a degradation of passivation behavior could be attributed to the increase in interface trap density caused by thermal damages.

N-type 결정질 실리콘 태양전지 응용을 위한 Al₂O₃ 박막의 패시베이션 특성 연구

정명일,최철종,Jeong, Myung-Il,Choi, Chel-Jong 한국결정성장학회 2014 한국결정성장학회지 Vol.24 No.3

Atomic layer deposition(ALD)을 이용하여 $Al_2O_3$ 박막을 형성하고 이에 대한 패시베이션 특성에 대한 연구를 수행하였다. ALD로 증착된 $Al_2O_3$ 박막은 $400^{\circ}C$ 5분간 후속 열처리 공정 후에도 $Al_2O_3$ - 실리콘 계면 반응 없이 비정질 상태를 유지할 만큼 구조적으로 안정한 특성을 나타내었다. 후속 열처리 후 $Al_2O_3$ 박막의 패시베이션 특성이 향상되었으며, 이는 field effective 패시베이션과 화학적 패시베이션 효과가 동시에 상승에 기인하는 것으로 판단된다. $Al_2O_3$ 박막의 음고정 전하를 정량적으로 평가하기 위해서 후속 열처리 공정을 거친 $Al_2O_3$ 박막을 이용하여 metal-oxide-semiconductor(MOS) 소자를 제작하고 capacitance-voltage(C-V) 분석을 수행하였다. C-V 결과로부터 추출된 flatband voltage($V_{FB}$)와 equivalent oxide thickness(EOT)의 관계식을 통하여 $Al_2O_3$ 박막의 고정음전하는 $2.5{\times}10^{12}cm^{-2}$로 계산되었으며, 이는 본 연구에서 제시된 $Al_2O_3$ 박막 공정이 N-type 실리콘 태양전지의 패시베이션 공정에 응용 가능하다는 것을 의미한다. The passivation property of $Al_2O_3$ thin film formed using atomic layer deposition (ALD) for the application of crystalline Si solar cells was investigated using microwave photoconductance decay (${\mu}$-PCD). After post-annealing at $400^{\circ}C$ for 5 min, $Al_2O_3$ thin film exhibited the structural stability having amorphous nature without the interfacial reaction between $Al_2O_3$ and Si. The post-annealing at $400^{\circ}C$ for 5 min led to an increase in the relative effective lifetime of $Al_2O_3$ thin film. This could be associated with the field effective passivation combined with surface passivation of textured Si. The capacitance-voltage (C-V) characteristics of the metal-oxide-semiconductor (MOS) with $Al_2O_3$ thin film post-annealed at $400^{\circ}C$ for 5 min was carried out to evaluate the negative fixed charge of $Al_2O_3$ thin film. From the relationship between flatband voltage ($V_{FB}$) and equivalent oxide thickness (EOT), which were extracted from C-V characteristics, the negative fixed charge of $Al_2O_3$ thin film was calculated to be $2.5{\times}10^{12}cm^{-2}$, of which value was applicable to the passivation layer of n-type crystalline Si solar cells.

저온에서 AlGaN/GaN HEMT의 전기적 특성 변화

강민성,박용운,최철종,양전욱,Kang, Min Sung,Park, Yong Woon,Choi, Cheol-Jong,Yang, Jeon Wook 한국전기전자학회 2018 전기전자학회논문지 Vol.22 No.2

AlGaN/GaN HEMT를 제작하여 상온에서 $-178^{\circ}C$의 저온에 이르기까지 트랜지스터의 전기적인 특성 변화를 연구하였다. 상온에서 264 mA/mm를 나타내던 게이트 길이 $2{\mu}m$인 HEMT의 드레인 전류는 온도의 감소에 따라 변화하여 $-108^{\circ}C$의 온도에서 388 mA/mm로 47%의 증가를 나타냈으며 최대 트랜스컨덕턴스는 121 mS/mm로 부터 183 mS/mm로 증가하였다. 또한 $-178^{\circ}C$의 온도에 이르기까지 -0.39 V의 문턱전압 변화를 보였다. 이러한 변화는 주로 상온에서부터 $-108^{\circ}C$의 온도에서 나타나고 있으며 온도감소에 따른 $720{\Omega}/sq.$ 로부터 $300{\Omega}/sq.$로 감소하는 면저항의 변화와 함께하고 있다. Low temperature variation of electrical characteristics for AlGaN/GaN/HEMT was studied. To investigate the effect of temperatures, transistor was cool down to $-178^{\circ}C$ and electrical characteristics were measured. The drain current density of an AlGaN/GaN HEMT with a gate length of $2{\mu}m$ was increased from 264 mA/mm to 388 mA/mm and the maximum transconductance was increased from 105 mS/mm to 134 mS/mm by decreasing the temperature to $-108^{\circ}C$. Also, the threshold voltage was shifted -0.39 V with the temperature. The reason for the variations was seemed to the reduced channel resistance corresponding to the temperature. However, most of the variation of the electrical characteristics takes places above $-108^{\circ}C$.

SiGe JFET과 Si JFET의 전기적 특성 비교

박병관,양현덕,최철종,심규환,Park, B.G.,Yang, H.D.,Choi, C.J.,Shim, K.H. 한국전기전자재료학회 2009 전기전자재료학회논문지 Vol.22 No.11

We have designed a new structures of Junction Field Effect Transistor(JFET) using SILVACO simulation to improve electrical properties and process reliability. The device structure and process conditions of Si control JFET(Si JFET) were determined to set cut off voltage and drain current(at Vg=0 V) to -0.46 V and $300\;{\mu}A$, respectively. Among many design parameters influencing the performance of the device, the drive-in time of p-type gate is presented most predominant effects. Therefore we newly designed SiGe JFET, in which SiGe layers were placed above and underneath of Si-channel. The presence of SiGe layer could lessen Boron into the n-type Si channel, so that it would be able to enhance the structural consistency of p-n-p junction. The influence of SiGe layer could be explained in conjunction with boron diffusion and corresponding I-V characteristics in comparison with Si-control JFET.

나노전자소자기술

장문규,김약연,최철종,전명심,박병철,이성재,Jang, M.G.,Kim, Y.Y.,Choi, C.J.,Jun, M.S.,Park, B.C.,Lee, S.G. 한국전자통신연구원 2005 전자통신동향분석 Vol.20 No.5

무어의 법칙을 근간으로 하는 전계효과 트랜지스터는 매 18개월마다 0.7배씩의 성공적인 소형화를 거듭하여 최근에는 50nm 크기로 구성된 약 1억 개의 트랜지스터가 집적된 칩을 생산하고 있다. 그러나 트랜지스터의 크기가 50nm 이하로 줄어들면서는 단순한 소형화 과정은 근본적인 물리적인 한계에 접근하게 되었다. 특히 게이트 절연막의최소 두께는 트랜지스터의 소형화에 가장 직접적인 중요한 요소이나, 실리콘 산화막의 두께가 2nm 이하가 되면서 게이트 절연막을 집적 터널링하는 전자에 의한 누설전류의 급격한 증가로 인하여 그 사용이 어려워지고 있는 추세이다. 따라서 본 논문에서는 트랜지스터의 소형화에 악영향을 미치는 물리적인 한계요소에 대하여 살펴보고, 이러한 소형화의 한계를 뛰어넘기 위한 노력의 일환으로 연구되고 있는 이중게이트 구조의 트랜지스터, 쇼트키 트랜지스터, 나노선을 이용한 트랜지스터 및 분자소자 등의 새로운 소자구도에 대하여 살펴보고자 한다.

SiGe/Si/SiGe Channel을 이용한 JFET의 전기적 특성

박병관,양현덕,최철종,김재연,심규환,Park, B.G.,Yang, H.D.,Choi, C.J.,Kim, J.Y.,Shim, K.H. 한국전기전자재료학회 2009 전기전자재료학회논문지 Vol.22 No.11

The new Junction Field Effect Transistors (JFETs) with Silicon-germanium (SiGe) layers is investigated. This structure uses SiGe layer to prevent out diffusion of boron in the channel region. In this paper, we report electrical properties of SiGe JFET measured under various design parameters influencing the performance of the device. Simulation results show that out diffusion of boron is reduced by the insertion SiGe layers. Because the SiGe layer acts as a barrier to prevent the spread of boron. This proposed JFET, regardless of changes in fabrication processes, accurate and stable cutoff voltage can be controlled. It is easy to maintain certain electrical characteristics to improve the yield of JFET devices.

Correlation of Reverse Leakage Current Conduction Mechanism and Electrostatic Discharge Robustness of Transient Voltage Suppression Diode

Daoheung Bouangeune,Sang-Sig Choi,최철종,길연호,양전욱,Deok-Ho Cho,심규환 대한금속·재료학회 2014 ELECTRONIC MATERIALS LETTERS Vol.10 No.5

Five transient voltage suppression (TVS) diodes with breakdown voltages (BV) of 6, 7, 11, 13 and 15 V have been developed using low-temperature (LT) epitaxy technology and an LT fabrication process. The electrostatic discharge (ESD) performance and temperature dependency of reverse leakage current are investigated by applying the IEC61000-4-2 (IEC) standard and an I-V-T analysis. The TVS diodes exhibited excellent ESD robustness, exceeding the standard ESD requirement of IEC level 4, 8 kV in contact discharge, while also maintaining the reverse leakage current level below 10−9 A. Excellent ESD performance was found to be relevant for lower breakdown voltage TVS diodes. The reverse leakage currents showed substantial changes in thermal activation energy from 0.43 to 0.6 eV with respect to BV control from 6 to 15 V. The increased activation energy at high BV was attributed to the transition of the conduction mechanism from tunneling mode to generation-recombination mode. The reduction of reverse leakage current from a generation-recombination to tunneling conduction mechanism is expected to improve the ESD performance of TVS diodes.

ICP 표면 처리된 Si 기판 위에 성장된 Ge 층의 초기 성장 상태 연구

양현덕,길연호,심규환,최철종,Yang, Hyun-Duk,Kil, Yeon-Ho,Shim, Kyu-Hwan,Choi, Chel-Jong 한국결정성장학회 2011 韓國結晶成長學會誌 Vol.21 No.4

We have investigated the effect of inductively coupled plasma (ICP) treatment on the early growth stage of heteroepitaxial Ge layers grown on Si(100) substrates using low pressure chemical vapor deposition (LPCVD), The Si(100) substrates were treated by ICP process with various source and bias powers, followed by the Ge deposition, The ICP treatment led to the enhancement in the coalescence of Ge islands, The growth rate of Ge on Si(100) with ICP surface treatment is about 5 times higher than that without ICP surface treatment. A missing dimer caused by the ICP surface treatment can act as a nucleation site for Ge adatoms, which could be responsible for the improvement in growth behavior of Ge on Si(100) substrates. Inductively Coupled Plasma(ICP)를 이용하여 다양한 조건으로 표면 처리한 Si(100) 기관 위에 Low Pressure Chemical Vapor Deposition(LPCVD)를 이용하여 Ge 층을 이종접합 성장하고, Ge 층 성장 초기의 표면 상태를 Scanning Electron Microscopy(SEM)을 통해 분석하였다. ICP를 이용하여 표면 처리된 Si(100) 기판 위에 성장된 Ge 층의 경우 ICP 처리하지 않은 시편보다 Ge 성장율이 약 5배 이상 증가되었다. ICP 처리된 시편의 Ge 성장률 증가는 ICP 표면 처리 공정으로 Si 기관 표면에서 떨어져 나간 missing dimer가 Ge adatom들에 핵을 형성할 자리를 제공하여 Ge island의 형성과 융합을 촉진시키는 것으로 사료된다.

Transient Voltage Suppressor Diode Designed for the Protection of High-brightness GaN-based LEDs from Various Electrostatic Discharge Shocks

BOUANGEUNEDAOHEUNG,Ye-Ji Lee,Jaehee Cho,심규환,최철종,Sang-Sik Choi,Deok-Ho Cho 한국물리학회 2014 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.65 No.7

Transient voltage suppressor (TVS) diodes were fabricated using low-temperature epitaxy technologyand were employed to improve the electrostatic discharge (ESD) strength of GaN lightemitting diodes (LEDs). The ESD performance and the protection capability of the TVS diodeswere investigated using various ESD simulators of the human body model (HBM), the IEC (InternationalElectrotechnical Commission) 61000-4-2 (IEC), and a transmission line pulse (TLP)analysis. According to the IEC, the manufactured TVS diode could withstand in excess of ±30kV without any degradation in the I-V characteristics; meanwhile, the GaN LED itself exhibitedcatastrophic degradation caused by weak ESD power. The GaN LED assembled with the TVSdiode had improved ESD robustness from ±3.8 kV to ±8 kV according to the HBM, from ±1.2 kVto > ±30 kV according to the IEC, and from 4.3 A to > ±30 A according to the TLP analysis. Furthermore, its performance was maintained perfect I-V manner with negligible changes in radiantpower, leakage current and breakdown voltage up to the limit of the ESD simulators. Namely, themanufactured TVS diodes were effective in the protection of sensitive GaN LEDs from very strongESD shocks.

RTCVD를 이용한 GeSn 에피층의 저온 성장기술

길연호(Yeon-Ho Kil),육심훈(Sim-Hoon Yuk),장한수(Han-Soo Jang),최철종(Chel-Jong Choi),임시종(See-Jong Leem),심규환(Kyu-Hwan Shim) 대한전자공학회 2016 대한전자공학회 학술대회 Vol.2016 No.11