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노인의 여가활동과 자원봉사활동 및 생활만족에 관한 연구
본 연구의 목적은 부산지역 거주 55세(고령자 고용촉진법 기준)이상의 노인을 대상으로 노인의 여가활동과 자원봉사활동 및 생활만족에 관한 차이분석과 상대적 영향력을 분석하는 데 있다. 연구를 위한 표본선정은 부산시 통계연보(2009)를 모집단으로 하여 유층표집과 집락표집을 하였다. 목표 표본 수는 1000명을 설정하였으며 유효한 표본 수는 865명이다. 자료 분석방법으로는 t-test와 일원변량분석(Scheffe검증), 그리고 변인 간 상관관계와 상대적 영향력을 알아보기 위하여 다중회귀분석을 실시하였다. 본 연구의 결과를 요약하면 다음과 같다. 첫째, 인구학적 특성에 따른 생활만족도에서는 교육수준이 낮을수록 생활만족도가 높으며, 가족관계적 특성에서는 배우자가 있는 노인들이 없는 노인들보다 생활만족도가 높은 것으로 나타났다. 사회경제적 특성에서는 생활수준이 높을수록, 수입이 되는 일을 할수록, 가족의 한 달 수입이 많을수록, 여가활동과 자원봉사활동 모두 참여하고 있을 때 생활만족도가 높게 나타났다. 둘째, 여가활동 참여에 따른 생활만족도에서는 여가활동유형 중 건강․스포츠 활동이 생활만족도가 가장 높은 것으로 나타났고, 여가활동 참여빈도가 높을수록, 여가활동 참여 기간이 길수록, 그리고 여가활동 만족도가 높을수록 노인의 생활만족도가 높게 나타났다. 셋째, 자원봉사활동 참여에 따른 생활만족도에서는 자원봉사활동 유형 중 경로당, 요양원 방문 봉사활동이 가장 높게 나타났으며, 자원봉사활동이 길수록, 자원봉사활동 만족도가 높을수록 노인의 생활만족도가 높게 나타났다. 넷째, 노인의 생활만족도를 설명하는 관련변인들의 변수 중에서는 성별, 연령, 건강상태, 생활수준, 현재 가족관계, 수입이 되는 일 유․무 변수가 통계적으로 유의한 것으로 나타났다. 다섯째, 노인의 여가 및 자원봉사활동 참여형태가 노인의 생활만족도에 미치는 상대적 영향력을 살펴보면 여가 및 자원봉사활동 모두 참여하지 않는 노인보다는 여가활동에만 참여<자원봉사활동에만 참여<자원봉사활동과 여가활동 모두 참여하는 노인들의 순으로 생활만족도가 높게 나타나 세 변수 모두 통계적으로 유의한 것으로 나타났다. 본 연구의 결과는 다음과 같은 제언을 가능하게 해 준다. 첫째, 노인을 소외되고 우울한 존재가 아닌 우리 사회의 역동적이고 유용한 인적 자원으로 여기는 인식전환을 위한 제도적 장치가 필요하다. 둘째, 고령사회의 문제를 예방․해결하고 노인의 생활만족도를 높이기 위해 노인의 여가활동과 자원봉사활동 참여를 활성화시키는 정부차원의 다각적인 정책적 지원이 요구된다. 셋째, 생활만족도가 낮거나 여가활동과 자원봉사활동에의 참여도가 낮은 여러 노인집단들을 여가활동, 자원봉사활동으로 유인하기 위한 노인기관 시설확충, 노인들의 요구가 반영된 다양한 프로그램 개발, 지도자 양성 및 교육 등이 요구된다. 넷째, 현재 여가활동과 자원봉사활동에 참여하고 있는 노인들의 지속적인 활동참여 유도와 동기 강화를 위해 명확한 활동목표 설정과 지속적 관리, 기관 간 네트워크 구축 등이 필요하다.
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고속 칩간 인터페이스의 분석을 위한 CMOS MIPI 송수신기 브리지 칩과 온 칩 모니터링 회로
In this thesis, CMOS bridge chips and an on-chip monitoring circuit are proposed to overcome the limitation of interface speed and to increase the reliability of test results in the evaluation of chip-to-chip high-speed interface. The proposed mobile industry processor interface (MIPI) C-PHY transceiver and D-PHY receiver bridge chips convert the signal transfer types and overcome the data transfer rate to interface the modules of the mobile camera and display with the test equipment. The proposed MIPI C-PHY transceiver bridge chip with three lanes, which is implemented using a 65-nm CMOS process with 1.2-V supply, supports a total bandwidth of 20.52 Gb/s. The MIPI C-PHY transmitter improves signal integrity by using the proposed impedance calibration and level-dependent pre-emphasis. The MIPI C-PHY receiver increases the time margin by using the proposed decision feedback equalizer (DFE)-based data dependent elastic buffer (DDEB), and performs a synchronized 3-to-21 deserialization. The level-dependent pre-emphasis proposed for the MIPI C-PHY transmitter improves the eye-width from 0.55 unit interval (UI) to 0.67 UI at data rate of 3 GSymbol/s/lane. In addition, the time jitter of the clock recovered in the MIPI C-PHY receiver is reduced from 118 ps to 90 ps by using the proposed DFE-based DDEB. The proposed MIPI D-PHY receiver bridge chip supports a data bandwidth of 20 Gb/s using four data lanes and one clock lane. The receiver bridge chip performs byte synchronization and 1-to-8 deserialization. The proposed auto-skew calibration has a simple architecture and is insensitive to dynamic noise by using the multiple bits supplied from the deserializer as a result of the phase detector. The proposed receiver bridge chip is implemented using a 0.11-μm CMOS process with 1.2-V supply. The measured peak-to-peak time jitter of the signal recovered is 50 ps at a data rate of 5.0 Gb/s/lane on the PCB FR-4 10-inch channel. The proposed skew calibration reduces the time skew among four data and one clock to less than 10 ps. An on-chip monitoring circuit is proposed for signal analysis of high-speed chip-to-chip interfaces. It consists of a fractional-N phase-locked loop (PLL)-based frequency synthesizer, a high-bandwidth track-and-hold circuit, and a 10-bit analog-to-digital converter (ADC) to implement a subsampling scheme. The on-chip monitoring circuit samples 49 points over 2 UIs of a high-speed input signal when the frequency multiplication of the frequency synthesizer is 6.125/6. This multiplication reduces the time jitter accumulated in the voltage-controlled oscillator of the fractional-N PLL-based frequency synthesizer. The proposed on-chip monitoring circuit is implemented with a 65-nm CMOS technology with 1.2-V supply. The 8-Gb/s chip-to-chip interface signal is reconstructed with time and voltage resolutions of 5.1 ps and 1.17 mV, respectively.
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압축냉각공기를 이용한 마이크로 연삭가공 특성 분석 및 최적화에 관한 연구
이필호 성균관대학교 일반대학원 2010 국내석사
Compressed chilly air has recently been used in the machining process to prevent the pollution from the machining fluid. The objective of this research is to characterize and optimize the micro-grinding process under the condition of compressed chilly air in the meso-scale micro-grinding machine tool system. Graph theory is introduced for design of meso-scale micro-grinding machine structure. The selected final configuration of meso scale micro-grinding machine structure is a horizontal one with the consideration of the uniform disposition from the kinematics point of view and the minimum mass motion. To characterize the effect of compressed chilly air on the micro-grinding performance, grinding force, tool wear patterns and surface roughness are measured according to the varying depth of cut, feed rate and temperature of compressed chilly air. The experimental results show the effectiveness of the compressed chilly air to increase tool life with decreased grinding forces in the micro-grinding process. Response surface method is introduced for obtaining optimal micro-grinding conditions. Central composite design is used for design of experiment and second order regression model. The regression functions of grinding force and surface roughness are derived with respect to depth of cut, feed speed and air temperature. The multi-objective optimization of grinding force, surface roughness and material removal rate is then carried out by introducing desirability functions. The grinding force, surface roughness and material removal rate estimated from the optimal grinding conditions are similar to those from experiments, and the reproducibility of regression model is verified.
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夏季 韓國東岸 海域의 地衡風의 特性 및 吹送流와의 關係를 알아보기 위해 1983, 84, 85年 8月의 日平均 海面氣壓 資料를 利用하여 地衡風을 求하고, 같은 기간의 GEK 表層觀測流速에서 海洋觀測 資料로부터 計算한 地衡流速을 減한 값을 吹送流로 看做하였다. 지형풍은 울릉도 및 포항기상관측소 관측바람과 各各 復素相關係數 0.80, 0.74로 대체로 일치함을 보였다. 風速에 있어서는 두 관측바람보다 1.7, 2.0배 强함을 보였으며, 지형풍에 대한 두 實測風의 方向은 울릉도가 12.5°, 포항이 18.6° 左偏向하는 것으로 分析되었다. 硏究期間 동안의 平均지형풍속은 8m/sec, 平均 취송류속은 16.3 cm/sec로 취송류는 지형중의 약 2% 크기를 갖는 것으로 나타났으며, 方向은 平均 26.5° 右偏向함을 보여 定性的으로 Ekman 理論과 부합됨을 밝혔다. The relationship between wind and wind driven current is investigated in the East Sea in summer. For these purpose, the geostrophic winds are calculated using the atmospheric pressure data, which are compared with the measured winds at some meteorologic stations along the coast. The wind driven components of current are obtained by substracting the geostrophic components of current from the GEK-measured surface current. Geostrophic components of current are calculated by using the dynamic method based on the oceanographic data. The measured (Ulreung-Do and Pohang) and calculated winds are good correlation with complex correlation coefficient 0.80 and 0.74 and deflection angle 12.5° and 18.6° to the left for Ulreung-Do and Pohang respectively. The calculated winds are about 1.7 and 2.0 times stronger than the measured winds for Ulreung-Do and Pohang respectively. For the period study the mean geostrophic wind speed is 8 m/sec, the mean wind driven current speed is 16.3 cm/sec giving the response ratio of about 2%. The wind driven current deflects about 26.5° to the right of the geostrophic wind proving the Ekman theory qualitatively.
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다중-위상 출력 클록을 가지는 125 MHz CMOS 클록 발생기
This thesis proposes 125 MHz CMOS clock generator with a multi-phase output clock to be used in digital system applications such as microprocessors, memory interfaces, and communications. This uses a delay-locked loop (DLL) architecture with 64-phase output clock or a phase-locked loop (PLL) architecture with 51-phase output clock. A 125 MHz 64-phase DLL is implemented for time recovery in a digital wire-line system. The proposed DLL architecture comprises a coarse-locking circuit added to a conventional DLL circuit, which consists of a delay line including a bias circuit, phase detector, charge pump, and loop filter. The proposed coarse-locking circuit reduces the locking time of the DLL and prevents harmonic locking, regardless of the duty cycle of the clock. In order to verify the performance of the proposed coarse-locking circuit, a 64-phase DLL with an operating frequency range of 40 to 200 MHz is fabricated using a 0.18-µm 1-poly 6-metal CMOS process with a 1.8 V supply. The measured root-mean-square (RMS) and peak-to-peak jitter of the output clock are 2.94 ps and 18.7 ps, respectively. The differential non-linearity (DNL) and integral non-linearity (INL) of the 64-phase output clock are measured to be -0.338/+0.164 LSB and -0.464/+0.171 LSB, respectively, at an operating frequency of 125 MHz. The area and power consumption of the implemented DLL are 0.3 mm2 and 25.7 mW, respectively. In order to generate 51-phase clock with a frequency of 125 MHz for a frequency synthesizer, the proposed PLL uses three voltage-controlled oscillators (VCOs) which are connected by resistors. Each VCO consists of 17 delay-cells. An resistor averaging scheme, which makes three VCOs to connect with each other, makes it possible to generates 51-phase clock of the same phase difference. The proposed PLL is implemented by using 65-nm 1-poly 9-metal CMOS process with a 1.0 V supply. The measured RMS and peak-to-peak jitter of the output clock are 3.90 ps and 24.4 ps, respectively. The operating frequency range is 15 to 210 MHz. The DNL and INL of the 51-phase output clock are measured to be -0.107/+0.104 LSB and -0.132/+0.063 LSB, respectively, at an operating frequency of 125 MHz. The area and power consumption of the implemented PLL are 580 × 160 µm2 and 3.48 mW, respectively.
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