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왕진석(Jin Suk Wang),조남인(Nam In Cho) 대한공업교육학회 1983 대한공업교육학회지 Vol.8 No.2
It is shown that efficient solar cells using oxide ZnO on single crystal silicon can be made by rf sputtering, The optical transparancy and ease of preparation of these films is excellent and the conductivity can easily be brought within the appropriate range of solar cell use by heat treatment in H₂. The transmission is typically 80 percent averaged over visible range. The open circuit voltage and fill factor is decreased, and the short circuit current is increased with increasing heat treatment temperature. The maximum conversion efficiency can be obtained when ZnO/Si device is heated at 350(℃) in H₂, 10 min and ZnO thickness is 5,000(Å).
드라이 에칭에 의한 손상에 Kaufman 이온원을 이용한 주소의 주입
왕진석(Jin Suk Wang) 대한공업교육학회 1985 대한공업교육학회지 Vol.10 No.2
It is shown that the damage created due to Ar ion beam etching can be removed by low energy hydrogen implantation wityout any heat treatment. Hydrogen implantation with beam energies ranging from 0.4 to 1.0 KeV were carried out for 15 min.
소프트 에러율에 대한 박막 트랜지스터형 정적 RAM의 신뢰성
김도우,왕진석,Kim Do-Woo,Wang Jin-Suk 한국전기전자재료학회 2006 전기전자재료학회논문지 Vol.19 No.6
We investigated accelerated soft error rate (ASER) in static random access memory (SRAM) cells of thin film transistor (TFT) type. The effects on ASER by cell density, buried nwell structure, operational voltage, and polysilicon-2 layer thickness were examined. The increase in the operational voltage, and the decrease in the density of SRAM cells, respectively, resulted in the decrease of ASER values. The SRAM chips with buried nwell showed lower ASER than those with normal well structure did. The ASER decreased as the test distance from alpha source to the sample increased from $7{\mu}m\;to\;15{\mu}m$. As the polysilicon-2 thickness increased up to $1000\;{\AA}$, the ASER decreased exponentially. In conclusion, the best condition for low soft error rate, which is essential to obtain highly reliable SRAM device, is to apply the buried nwell structure scheme and to fabricate thin film transistors with the thick polysilicon-2 layer