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반도체소자의 고속마킹검사를 위한 vision system 개발
노영동,주효남,김주식 湖西大學校 工業技術硏究所 2005 工業技術硏究所論文集 Vol.24 No.-
In this paper, we propose the high speed making/surface inspection algorithm, that use adaptive automatic acquisition algorithm and real time matching algorithm of model data. The proposed automatic acquisition algorithm to obtain the adaptive model data extracts the interesting regions to fit in semiconductor characteristics, and create models of several semiconductor regardless of position and type. The proposed teal time matching algorithm uses geometrical pattern matching method to minimize effect of external environment of making/surface and only use semiconductor characteristic information. The proposed system has faster processing time than the conventional method. Also the proposed one has a good performance.
반도체 소자의 논리결함검출을 위한 pattern generator 회로설계에 관한 연구
노영동,김준식 호서대학교 반도체제조장비국산화연구센터 2003 학술대회 자료집 Vol.2003 No.1
반도체 소자의 집적도의 발전에 따라 생산과정에서의 기능적인 오류 검사 소요시간이 증가하게 되어 비용절감에 커다란 장애 요인이 되고 있다. 이러한 문제점을 효과적으로 처리하기 위하여 일괄적인 패턴과 어드레스를 발생시키는 pattern generator를 연구하였다.
노영동,김준식,Roh, Young-Dong,Kim, Joon-Seek 한국조명전기설비학회 2004 조명·전기설비학회논문지 Vol.18 No.6
일반적으로 반도체 소자의 집적도가 증가함에 따라 기능적 오류 검사 시간이 급격하게 증가하며, 이러한 문제를 해결하기 위해 제조공정에서 패턴 발생기의 사용은 필수적이다. 본 논문에서는 반도체 소자의 기능적 오류를 검사 하기 위한 패턴 발생기의 PLD(Programmable Logic Device) 회로를 설계하였다. 이러한 모든 사항은 시뮬레이션을 통하여 회로의 동작과 기능을 검증하였으며, 만족할만한 결과를 얻었다. Usually, according as accumulation degree of semi-conductor element increases, dynamic mistake test time increases sharply, and use of pattern generator is essential at manufacturing process to solve these problem. In this paper, we designed the PLD(Programmable Logic Device) circuit of pattern generator to examine dynamic mistake of semi-conductor element. Such all item got result that is worth verified action of return trip and function through simulation, and satisfy.
PLD 소자를 이용한 programmable delay 회로 설계
노영동,김준식 湖西大學校工業技術硏究所 2003 工業技術硏究所論文集 Vol.22 No.-
In the signal progresses, time delay can happen, and bring the operation error by the delay. Digital signal sets the timing to clock signal that get into ordinary standard. The delay of signal can bring the operational fatal error by that high speed digital system achieves CPU, RAM, ROM, FPGA and interface ICS and organic action fast usually. Skew can happen by such delayed signals and the serious problem in signal progresses can be happened on the semiconductor device testing or other digital circuit operating by the skew. To solve these problems, the device that make the exact delay must be used. To make a exact delay can be done by using delay components. However, many delay components must be used in the circuit design for complex delay structure. In this paper, we propose the programmable delay method/circuit using PLD device. The proposed method has many advantages, because that uses interior gates of PLD device from 1㎱ to several ㎱ delay the circuit designer can do programming voluntarily, and prove precision.
반도체소자의 고속마킹검사를 위한 vision system 개발
노영동(Woung-Dong Noh),주효남(Hyo—,Nam Joo),김준식(Joon—,oeek Kim) 호서대학교 공업기술연구소 2005 공업기술연구 논문집 Vol.24 No.1
In this paper, we propose the high speed making/surface inspection algorithm, that use adaptive automatic acquisition algorithm and real time matching algorithm of model data. The proposed automatic acquisition algorithm to obtain the adaptive model data extracts the interesting regions to fit in semiconductor characteristics, and create models of several semiconductor regardless of position and type. The proposed real time matching algorithm uses geometrical pattern matching method to minimize effect of external environment of making/surface and only use semiconductor characteristic information. The proposed system has faster processing time than the conventional method. Also the proposed one has a good performance.
PLD 소자를 이용한 programmable delay 회로 설계
노영동(Young-Dong Roh),김준식(Joon-Seek Kim) 호서대학교 공업기술연구소 2003 공업기술연구 논문집 Vol.22 No.1
In the signal progresses, tim e delay can happen, and bring the operation error by the delay. D ig ital signal sets the tim in g to clock signal th a t get into ordinary standard. T he delay of signal can bring the operational fatal error by th at h ig h speed d ig ita l system achieves CPU , R A M , R O M , F P G A and interface IC s and organic action fast usually, c^kew can happen by such delayed signals and the serious problem in signal progresses can be happened on the sem iconductor device testing or other dig ital circuit operating by the skew. T o solve these problem s, the device th at m ake the exact delay m ust be used. T o m ake a exact delay can be done by using delay com ponents. How ever, m any delay com ponents m ust be used in the circuit design for com plex delay structure. In this paper, w e propose the program m able delay m ethod/circuit using P L D device. T he proposed m ethod has m any advantages, because th at uses interior gates of P L D device from Ins to several ns delay the circuit designer can do program m ing voluntarily, and prove precision.
Effects of Rutaecarpine on the Metabolism and Urinary Excretion of Caffeine in Rats
노금한,정태천,Young Min Seo,이상규,Sudeep R. Bista,Mi Jeong Kang,장영동,김은영,강원구 대한약학회 2011 Archives of Pharmacal Research Vol.34 No.1
Although rutaecarpine, an alkaloid originally isolated from the unripe fruit of Evodia rutaecarpa, has been reported to reduce the systemic exposure of caffeine, the mechanism of this phenomenon is unclear. We investigated the microsomal enzyme activity using hepatic S-9 fraction and the plasma concentration-time profiles and urinary excretion of caffeine and its major metabolites after an oral administration of caffeine in the presence and absence of rutaecarpine in rats. Following oral administration of 80 mg/kg rutaecarpine for three consecutive days, caffeine (20 mg/kg) was given orally. Plasma and urine were collected serially for up to 24 h and the plasma and urine concentrations of caffeine and its metabolites were measured,and compared with those in control rats. The areas under the curve of both caffeine and its three major metabolites (paraxanthine, theophylline, and theobromine) were significantly reduced by rutaecarpine, indicating that caffeine was rapidly converted into the desmethylated metabolites, and that those were also quickly transformed into further metabolites via the hydroxyl metabolites due to the remarkable induction of CYP1A2 and 2E1. The significant induction of ethoxyresorufin O-deethylase, pentoxyresorufin O-depentylase, and p-nitrophenol hydroxylase strongly supported the decrease in caffeine and its major metabolites in plasma, as well as in urine. These results clearly suggest that rutaecarpine increases the metabolism of caffeine, theophylline, theobromine, and paraxanthine by inducing CYP1A2 and CYP2E1 in rats.
논리결함 검사를 위한 Pattern Generator의 PLD 회로 설계
김준식,노영동 한국반도체디스플레이기술학회 2003 한국반도체장비학회지 Vol.2 No.4
In this paper, we design the pattern generator circuits using PLDs(Programmable Logic Devices). The pattern generator is the circuit which generates the test pattern signal for the inspection of logical defects of semiconductor products. The proposed circuits are designed by the PLD design tool(MAX+ II of ALTERA). Also the designed circuits are simulated for the verification of the designed ones. The simulation results have a good performance.