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디지탈 위상 검출기에서의 Metastability 향상에 관한 연구
홍국태,이성대,정강민 成均館大學校 科學技術硏究所 1995 論文集 Vol.46 No.2
This paper shows our study on memory phase detectors, ie digital phase detectors using flipflops. For the purpose of improving metastability performance and delay performance, structure of circuits was designed to have better metastability and aspect ratio was controlled in order to give better delay performance.
洪國泰,李成大,鄭康敏 成均館大學校 科學技術硏究所 1994 論文集 Vol.45 No.2
In this paper, a programmable high-sample-rate FIR digital filter was designed for a highbandwidth communication system. A fully parallel bit-level pipelined transpose-form carrysave architecture using CSD coefficients was adopted for high-speed operation. In this system, multiplication can be translated to simple shift-addition processes. For programmability of filter coefficients, two decoders and a few registers are added, and the shifting processes of input data are controlled according to the data registered. Therefore, the speed performance of the designed filter is comparable to the case of a non- programmable filter.
홍국태,이성대,정강민 成均館大學校 科學技術硏究所 1995 論文集 Vol.46 No.1
In this paper, a high speed, high accuracy sample and hold circuit that minimizes the hold step error by using a new circuit architecture is proposed. This new sample-and-hold scheme takes advantages of the speed of the open loop sample-and-hold circuit in the SAMPLE time and the cancellation of charge injection in the HOLD time. It operates above 50MHz with 0.3mV hold step error.
∑$\Delta$ 변환기 후단 처리용 고선형 저전력 연속시간 필터의 설계
홍국태,정현택,손한웅,염왕섭,정강민 한국통신학회 1997 韓國通信學會論文誌 Vol.22 No.7
This paper introduces a monolithic chip 3.3V high-performance continuous-tune filter used in a CDP that can reconstruct the PDM or PWM signal output of a .SIGMA..DELTA. D/A converter. We also mentioned an active RC filter structure and filter order satisfying high-linearity and the design specification. In desigining the OP-AMP, using a structure that accepts some distortion we could reduce the chip area, and reducing the DC path using a new biascircuit gave us better power performance. The designed.SIGMA..DELTA. D/A converter post-processing filter does its smoothering operations and reconstructs the data without reducing the performance of the system.
양한유,홍국태,정강민 成均館大學校 科學技術硏究所 1992 論文集 Vol.43 No.2
본 연구는 외부조건의 영향을 적게 받고 일정한 전류를 발생시켜 주는 CMOS 전류표준 회로를 설계하였다. 이 회로에서 기존에 통상 사용되어 왔던 PTAT 전압원 대신에 특히 온도변화에 독립적인 구조로서 부동전압원에 CMOS 전압표준을 사용한 구조를 제시하였다. 이로서 회로의 정확성, 간결성을 향상시킬수 있다. 시뮬레이션을 통하여 회로의 작동을 검증하고 성능을 토의 하였다. In this work, a CMOS current reference circuit is designed, which is independent of variations of external parametters. A circuit configuration using CMOS voltage reference is suggested and it is shown that this circuit is less sensitive, especially to the temperature variations, compared to the PTAT voltage source. Through simulations, the operation of the circuit is verified and its performance is discussed.
집적된 수동 소자 변동에 의한 RC 시상수 자동 보정 기법
이성대,홍국태,장명준,정강민 한국센서학회 1997 센서학회지 Vol.6 No.2
In this paper, on-chp atomatic tuning circuit, using proposed integration level approximation technique, is designed to tuning of the variation of RC time-constant due to aging or temperature variation, etc. This circuit reduces the error, the difference between code values and real outputs of integrator, which is drawback of presented dual-slope tuning circuit and eliminates modulations of processing signals in integrated circuit due to fixed tuning codes during ordinary operation. This system is made up of simple integrator, A/D converter and digital control circuit and all capacitors are replaced by programed capacitor arrays in this system. This tuning circuit with 4 bit resolution achieves -9.74 ∼ +9.68% of RC time constant error for 50 resistance variation.
이성대,홍국태,정강민,Lee, Seong-Dae,Hong, Guk-Tae,Jeong, Gang-Min 한국정보처리학회 1995 정보처리논문지 Vol.2 No.1
A 8-bit 15MHz CMOS subranging Analog-to-Digital converter for high-speed, low-power consumption applications is described. Subranging, 2 step flash, A/D converter used a new resistor string and a simple comparator architecture for the low power consumption and small chip area. Comparator exhibites 80dB loop gain, 50MHz conversion speed, 0.5mV offset and maximum error of voltage divider was 1mV. This Analog-to-Digital converter has been designed and fabricated in 1.2 m N-well CMOS technology. It consumed 150mW power at +5/-5V supply and delayed 65ns. The proposed Analog-to-Digital converter seems suitable for high- speed, low-power consumption, small area applications and one-chip mixed Analog- Digital system. Simulations are performed with PSPICE and a fabricated chip is tested. 이 논문에서는 고속 저전력 분야에 적용하기 위한 8비트, 15MHz A/D 변환기 설계 에 관해 기술한다. 2단 플래시 방식인 서브레인징 구조 A/D 변환기에서 칩 면적을 줄 이기 위해 저항의 수를 감소시킨 전압분할 회로를 설계하였다. 비교기는 80 dB의 이득, 50 MHz의 대역폭, 오프셋 전압이 0.5mV이고, 전압분할 회로의 최대오차는 1mV이다. 설계된 A/D변환기는 +5/-5V 공급 전압에 대해 전력소비가 150mW, 지연시간이 65ns 이다. A/D 변환기는 N-well공정을 이용하여 설계하고, 제작하였다. 제안된 변환기는 고속, 저전력, 소형 단일 칩 아날로그-디지탈 혼합 시스템 응용에 적합하다. 시뮬레이 션은 PSPICE를 이용하여 수행하였고, 1차 가공된 칩을 데스트 하였다.