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Selective Si Epitaxy for Device Isolation
양전욱,조경익,박신종,Yang, Jeon Wook,Cho, Kyoung Ik,Park, Sin Chong The Institute of Electronics and Information Engin 1986 전자공학회논문지 Vol.23 No.6
The effect of SiH2Cl2 -HCl gas on the growth rate of epitaxial layer is studied. The temperature, pressure and gas mixing ratio of SiH2Cl2 and HCl are varied to study the growth rate dependence and selective Si epitaxy. The P-n junction diode is fabricated on the epitaxial layer and electrical characteristics are examined. Also, using selective Si epitaxy, a possibility of thin dielectric isolation process, that gives an independent isolation width on the mask dimension, is examined.
A Study on the Electrical Characteristics of Oxide Grown from Phosphorus-Doped Polysilicon
윤형섭,강상원,박신종,Yoon, Hyung Sup,Kang, Sang Won,Park, Sin Chong The Institute of Electronics and Information Engin 1986 전자공학회논문지 Vol.23 No.6
In this work the electrical conduction and breakdown properties of thermal oxides grown on phosphorus-doped polysilicon have been investigated by using ramped I-V measurements. The oxide films, grown from phosphorus-doped polysilicon deposited at 560\ulcorner, have higher breakdown field(6.8MV/cm) and lower leakage current than those deposited at 625\ulcorner. Also the effective energy barrier height(\ulcorner)calculated from the Fowler-Nordheim curve of polyoxide was 0.76eV for 560\ulcorner deposited film and 0.64eV for 625\ulcorner deposited film.
A Design of Ion-Implanted GaAs MESFET's Having High Transconductance Characteristics
이창석,심규환,박형무,박신종,Lee, Chang Seok,Shim, Gyu-Hwan,Park, Hyung Moo,Park, Sin-Chong The Institute of Electronics and Information Engin 1986 전자공학회논문지 Vol.23 No.6
포화속도 모델을 이용하여 이온주입공정에 의한 GaAs MESFET를 설계하였다. 20KeV의 $Si^+$ 이온 주입공정과 $975^{\circ}C$ 5sec의 RTP 활성화공정에 의해 $V_{th}$가 -0.5V 일때의 gm이 460ms/mm인 MESFET를 설계할 수 있었다. The current-voltage characteristics of ion-implanted GaAs MESFET's have been simulated by using the velocity saturation model. Using this model, a MESFET with threshold voltage of -0.5V and transconductance of 460 mS/mm is designed. To implement high transconductance MESFET's, low energy ion-implantation (20 keV) and RTP(Rapid Thermal Process) activation ($575^{\circ}C$, 5sec) processes are required.
Electrical Characteristics of Trench Capacitor with Various Structures
이진희,남기수,김말문,박신종,Lee, Jin Hee,Nam, Kee Soo,Kim, Mal Moon,Park, Sin Chong The Institute of Electronics and Information Engin 1987 전자공학회논문지 Vol.24 No.1
Trench capacitors with four different structures were fabricated using plasma and reactive ion etching technique, and evaluated using their C-V and I-V characteristics. The results shows that the two step plasma etching technique is the best method to fabricate the trench capacitor because of its high breakdown field (~7.75 MV/Cm) and good step coverage. And the fixed oxide charges are comparable between the trench (3.6xE10/Cm\ulcorner~7.5xE10/Cm\ulcorner and the planar(4.5xE10/Cm\ulcorner~6.5E10/Cm\ulcorner capacitors.