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Inner-Gate-Engineered GAA MOSFET to Enhance the Electrostatic Integrity
Biswajit Jena,Sidhartha Dash,Soumya Ranjan Routray,Guru Prasad Mishra 성균관대학교(자연과학캠퍼스) 성균나노과학기술원 2019 NANO Vol.14 No.10
Gate-all-around (GAA) MOSFETs are the best multi-gate MOSFET structure due to their strong electrostatic control over the channel. The electrostatic controllability can be enhanced further by applying some gate engineering technique to the existing GAA structure. This paper investigates the effect of inner gate (core gate) on the electrostatic performance of conventional GAA MOSFET. The inner gate engineering increases both the electrostatic control and packing density of GAA MOSFET. In this paper, we have presented an inner-gate-engineered (IGE) GAA MOSFET and inspected its advantages over conventional counterparts. The proposed structure exhibits higher I on/I off ratio, low threshold voltage and improved RF performances as compared to the conventional structure. Analytic simulation has been carried out for numerous figures of merit (FOMs) for different technology nodes.
Junctionless Sandwiched-gate Logic Design using Novel Device Structure
Myunghwan Ryu,Youngmin Kim 대한전자공학회 2018 Journal of semiconductor technology and science Vol.18 No.4
In this paper, a novel sandwiched-gate logic family that is based on a sandwiched-gate inverter, which consists of an NMOS Gate-All-Around (GAA) together with a donut-type PMOS GAA, is proposed. For the realization of the proposed vertical structure, a junctionless configuration is suggested with the absence of the channel- doping process. The ratio of the thickness of the NMOS and the PMOS determines the switching threshold in the sandwiched-gate inverter. The direct-current (DC) operation and the transient performance of the sandwiched-gate inverter are investigated with 3D technology computer-aided-design (TCAD) simulations. The sandwiched- gate inverter exhibits a correct inverter operation with a high noise margin and a fast transition speed. To extend the proposed architecture to other logic gates, the proposed sandwiched-gate structure is also applied to fundamental logic circuits such as the NAND, NOR, and SRAM cell designs, and each operation is verified. The proposed logic gates achieve up to a 20% area reduction compared with the conventional GAA.
서재화,윤영준,이승민,이정희,조성재,강인만 한국물리학회 2015 Current Applied Physics Vol.15 No.3
In this work, a Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET) has been designed and analyzed. Various studies on IIIeV compound semiconductor materials for applications in TFET devices have been made and we adopt one of them to perform a physical design for boosting the tunneling probability. The GAA structure has a partially open region for extending the tunneling area and the channel is under the GAA region, which makes it an arch-shaped GAA structure. We have performed the design optimization with variables of epitaxy channel thickness (tepi) and height of source region (Hsource) in the Si-based TFET. The designed arch-shaped GAA TFET based on Si platform demonstrates excellent performances for low-power (LP) applications including on-state current (Ion) of 694 mA/mm, subthreshold swing (S) of 7.8 mV/dec, threshold voltage (Vt) of 0.1 V, current gain cut-off frequency (fT) of 12 GHz, and maximum oscillation frequency (fmax) of 283 GHz.
Novel Vertical GAA-AlGaN/GaN Dopingless MIS-HEMT: Proposal and Investigation
Ravi Ranjan,Nitesh Kashyap,Ashish Raman 한국전기전자재료학회 2021 Transactions on Electrical and Electronic Material Vol.22 No.4
This paper presents a gate all around (GAA) AlGaN/GaN HEMT (GAA-MIS-HEMT) with AlN as an interfacial passivation layer. Gate all around technique is used to improve the performance of device such as carrier concentration, electric field and current density at the interface of AlGaN & GaN. The enhanced control over the 2DEG due to gate all around structure helped in attaining superior performance. Al2O3 is used as a dielectric. The results of GAA-MIS-HEMT are compared with planar-MIS-HEMT, which shows that the GAA-MIS-HEMT provides better ON-state current, OFF-state current, transconductance, cutoff frequency (11 GHz) and ON-state to OFF-state current ratio (10 11 ), ON-resistance (0.9Ω-cm2 ) and subthreshold slope (63 mV/dec). All the layers of proposed structure are dopingless.
Seo, J.H.,Yoon, Y.J.,Lee, S.,Lee, J.H.,Cho, S.,Kang, I.M. Elsevier 2015 Current Applied Physics Vol.15 No.3
In this work, a Si-based arch-shaped gate-all-around (GAA) tunneling field-effect transistor (TFET) has been designed and analyzed. Various studies on III-V compound semiconductor materials for applications in TFET devices have been made and we adopt one of them to perform a physical design for boosting the tunneling probability. The GAA structure has a partially open region for extending the tunneling area and the channel is under the GAA region, which makes it an arch-shaped GAA structure. We have performed the design optimization with variables of epitaxy channel thickness (t<SUB>epi</SUB>) and height of source region (H<SUB>source</SUB>) in the Si-based TFET. The designed arch-shaped GAA TFET based on Si platform demonstrates excellent performances for low-power (LP) applications including on-state current (I<SUB>on</SUB>) of 694 μA/μm, subthreshold swing (S) of 7.8mV/dec, threshold voltage (V<SUB>t</SUB>) of 0.1 V, current gain cut-off frequency (f<SUB>T</SUB>) of 12 GHz, and maximum oscillation frequency (f<SUB>max</SUB>) of 283 GHz.
Simulation study on effect of drain underlap in gate-all-around tunneling field-effect transistors
Jae Sung Lee,서재화,조성재,이정희,강신원,배진혁,조의식,강인만 한국물리학회 2013 Current Applied Physics Vol.13 No.6
In this work, the effects of underlapping drain junction on the performances of gate-all-around (GAA)tunneling field-effect transistors (TFETs) have been studied in terms of direct-current (DC) characteristics including on-current (Ion), off-current (Ioff), subthreshold swing (S), and Ion/Ioff ratio. In addition, the dependences of intrinsic delay time (s) and radio-frequency (RF) performances including cut-off frequency (fT) and maximum oscillation frequency (fmax) on gateedrain capacitance (Cgd) with the underlapping were investigated as the gate length (Lgate) is scaled. A GAA TFET with asymmetric junctions, with an underlap at the drain side, demonstrated DC and RF performances superior to those of a device with symmetric junctions.
Simulation study on effect of drain underlap in gate-all-around tunneling field-effect transistors
Lee, J.S.,Seo, J.H.,Cho, S.,Lee, J.H.,Kang, S.W.,Bae, J.H.,Cho, E.S.,Kang, I.M. Elsevier 2013 Current Applied Physics Vol.13 No.6
In this work, the effects of underlapping drain junction on the performances of gate-all-around (GAA) tunneling field-effect transistors (TFETs) have been studied in terms of direct-current (DC) characteristics including on-current (I<SUB>on</SUB>), off-current (I<SUB>off</SUB>), subthreshold swing (S), and I<SUB>on</SUB>/I<SUB>off</SUB> ratio. In addition, the dependences of intrinsic delay time (τ) and radio-frequency (RF) performances including cut-off frequency (f<SUB>T</SUB>) and maximum oscillation frequency (f<SUB>max</SUB>) on gate-drain capacitance (C<SUB>gd</SUB>) with the underlapping were investigated as the gate length (L<SUB>gate</SUB>) is scaled. A GAA TFET with asymmetric junctions, with an underlap at the drain side, demonstrated DC and RF performances superior to those of a device with symmetric junctions.
Joule Heating to Enhance the Performance of a Gate-All-Around Silicon Nanowire Transistor
Chang-Hoon Jeon,Jun-Young Park,Myeong-Lok Seol,Dong-Il Moon,Jae Hur,Hagyoul Bae,Seung-Bae Jeon,Yang-Kyu Choi IEEE 2016 IEEE transactions on electron devices Vol.63 No.6
<P>Thermal engineering assisted by electrical annealing was applied to enhance the device performance of a gate-all-around (GAA) silicon nanowire (Si-NW) transistor. The ON-state current is increased by four times. Joule heating was produced in a Si-NW by electrical biasing. The heating was concentrated on both edges of the gate, which served as a heat sink, effectively lowering the parasitic external resistance of the GAA Si-NW transistor. The electrical biasing gives rise to a thermal annealing effect on a selected device and to all devices connected by a common biasing electrode. The evidence reported in our previous work regarding current-induced oxidation by Joule heating in a Si-NW was also observed in the measured transfer characteristics of the GAA Si-NW transistor in this paper.</P>
Myoung-Sun Lee,Sung-Min Joe,Jang-Gn Yun,Hyungcheol Shin,Byung-Gook Park,Sang-Sik Park,Jong-Ho Lee 대한전자공학회 2012 Journal of semiconductor technology and science Vol.12 No.3
The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps (NIT). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of NIT originated by the movement of hydrogen species (h<SUP>*</SUP>) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the NIT generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated NIT.
Lee, Myoung-Sun,Joe, Sung-Min,Yun, Jang-Gn,Shin, Hyung-Cheol,Park, Byung-Gook,Park, Sang-Sik,Lee, Jong-Ho The Institute of Electronics and Information Engin 2012 Journal of semiconductor technology and science Vol.12 No.3
The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.