고 Gb/Chip을 위한 Pole이 추가된 MRAM의 최적 설계에 관한 연구

김동석(Dong Sok Kim),원혁(Hyuk Won),박관수(Gwan Soo Park) 한국자기학회 2008 韓國磁氣學會誌 Vol.18 No.3

Magnetoresistive random access memory (MRAM) don't get very public face on the field of non-volatile memory. Because recording capacity of MRAM is smaller than other non-volatile memory and structurally, magnetic efficiency of MRAM is very bad. We diminish a size of one cell in order to make MRAM of high recording capacity. But It don't make high recording field in general structures consisting of two current wire. Accordingly, We make a cell of small size is impossible. In this paper, we suggest new MRAM that it have two pole of high permeability on both ends of recording layer. Because magnetic efficiency of new MRAM is higher than exiting MRAM, it can make high recording field. And we can diminish the size of one cell due to recording layer of high coercivity. We used three-dimension finite element method to prove the reliability.

Local Field Switching 방식의 MRAM 설계

이감영(Gamyoung Lee),이승연(Seungyeon Lee),이현주(Hyunjoo Lee),이승준(Seungjun Lee),신형순(Hyungsoon Shin) 대한전자공학회 2008 電子工學會論文誌-SD (Semiconductor and devices) Vol.45 No.8

본 논문에서는 새로운 스위칭 방식인 LFS (Local Field Switching)을 이용하여 설계한 128비트 MRAM (Magnetoresistive Random Access Memory)에 대해 기술하였다. LFS 방식은 MTJ (Magnetic Tunnel Junction)를 직접 통과해 흐르는 전류에 의해 형성되는 국소 자기장을 이용하여 MTJ의 극성을 변환시킨다. 이 방식은 MTJ와 전류의 거리가 가깝기 때문에 작은 전류로도 충분히 큰 자기장을 형성하므로 writing current가 적어도 된다. 또한 Digit Line이 없어도 되므로 half select disturbance가 발생하지 않아 기존 MTJ를 이용한 방식에 비해 셀 선택도가 우수하다. 설계한 MRAM은 1T(트랜지스터)-1MTJ의 메모리 셀 구조를 가지며 양방향 write driver와 mid-point reference cell block, current mode sense amplifier를 사용한다. 그리고 MTJ 공정 없이 회로 동작을 확인하기 위해 LFS-MTJ cell을 CMOS emulation cell로 대체하였다. 설계한 회로를 6 metal을 사용하는 0.18㎛ CMOS 공정으로 구현하였고 제작된 chip을 custom board 상에서 테스트하여 동작을 확인하였다. In this paper, we describe a design of a 128bit MRAM based on a new switching architecture which is Local Field Switching(LFS). LFS uses a local magnetic field generated by the current flowing through an MTJ. This mode reduces the writing current since small current can induce large magnetic field because of close distance between MTJ and the current. It also improves the cell selectivity over using conventional MTJ architecture because it doesn't need a digit line for writing. The MRAM has 1-Transistor 1-Magnetic Tunnel Junction (1T-1MTJ) memory cell structure and uses a bidirectional write driver, a mid-point reference cell block and a current mode sense amplifier. CMOS emulation cell is adopted as an LFS-MTJ cell to verify the operation of the circuit without the MTJ process. The memory circuit is fabricated using a 0.18 ㎛ CMOS technology with six layers of metal and tested on custom board.

MRAM용 HSPICE 마크로 모델과 midpoint reference 발생 회로에 관한 연구

이승연,이승준,신형순 대한전자공학회 2004 電子工學會論文誌-SD (Semiconductor and devices) Vol.41 No.8

MRAM (Magneto-resistive Random Access Memory)은 자성체의 스핀 방향을 정보원으로 하는 비휘발성 메모리로 magneto-resistance 물질을 정보 저장 소자로 사용한다. 본 논문에서는 MRAM 시뮬레이션시 MTJ (Magnetic Tunneling Junction)의 hysteretic 특성, asteroid 특성, R-V 특성을 HSPICE에서 재현할 수 있는 새로운 macro-model을 제안하고 HSPICE에 적용하여 그 정확도를 검증하였다. 또한 종래의 reference cell 회로에 비하여 정확한 중간 저항 값을 유지하는 새로운 reference cell 회로를 제안하고 이를 본 논문에서 제안한 macro-model을 이용하여 검증하였다. MRAM uses magneto-resistance material as a storage element, which stores cell data as a polarization of spin in a free magnetic layer. This magneto-resistance material has hysteresis, asteroid curve at the thermal variation, and R-V characteristics for switching the data. Therefore, a macro-model which can reproduce these characteristics is required for MRAM simulation. We propose a macro-model of TMR (Tunneling Magneto Resistance) that can reproduce all of these characteristics on HSPICE. Also we propose a novel sensing scheme, which generates reference resistance having the medium value, ( $R_{H}$+ $R_{L}$)/2, for a wide range of applied voltage and present simulation results based on the HSPICE macro-model of MTJ that we have developed.d.d.

MRAM 기반 SSD 파일 시스템의 에너지 효율적 서브페이징

이재열,한재일,김영만 한국IT서비스학회 2013 한국IT서비스학회지 Vol.12 No.4

The advent of the state-of-the-art technologies such as cloud computing and big data processing stimulates the provision of various new IT services, which implies that more servers are required to suppart them. However, the need for more servers will lead to more energy consumption and the efficient use of energy in the computing environment will become more important. The next generation nonvolatile RAM has many desirable features such as byte addressability, low access latency, high density and low energy consumption. There are many approaches to adopt them especially in the area of the file system involving storage devices, but their focus lies on the improvement of system performance, not on energy reduction. This paper suggests a novel approach for energy reduction in which the MRAM-based SSD is utilized as a storage device instead of the hard disk and a downsized page is adopted instead of the 4KB page that is the size of a page in the ordinary file system. The simulation results show that energy efficiency of a new approach is very effective in case of accessing the small number of bytes and is improved up to 128 times better than that of NANO Flash memory.

스핀전달토크형 자기저항메모리(STT-MRAM) 기술개발 동향

김도균(D. K. Kim),조지웅(J. U. Cho),노수정(S. J. Noh),김영근(Y. K. Kim) 한국자기학회 2009 韓國磁氣學會誌 Vol.19 No.1

Reduction of the critical current density (Jc) for STT magnetization switching is most important issue of magnetic tunnel junctions (MTJs) based MRAM. This report describes how to decrease the Jc and will introduce the recent research progresses of STT-MRAM devices with material engineering and structural improvement, respectively.

High-performance Sum Operation with Charge Saving and Sharing Circuit for MRAM-based In-memory Computing

Jangseok Yu,Geonwoo Lee,Taehui Na 대한전자공학회 2024 Journal of semiconductor technology and science Vol.24 No.2

In the era of big data, Von Neumann architectures, with their separation of processor and memory, face limitations in terms of bandwidth and data movement overhead. MRAM-based in-memory computing (IMC) is a promising approach to address these issues, leveraging MRAM to perform simple logical operations directly within memory. However, implementation of n-bit full adder (FA) using pre-charge sense amplifier requires “n + 1” stages. Although carry lookahead adders can reduce the number of stages, it causes significant area overhead, which makes them unsuitable for IMC applications. Therefore, it is important to explore alternatives that can minimize the number of stages. In this paper, we propose a high-performance multi-bit FA utilizing a charge saving and sharing (CSS) circuit that acquires a carry every 4 bits and performs a sum operation every 4 bits in parallel. The CSS circuit-based FA reduces the number of stages to “n/4 + 5”, while minimizing the associated area overhead.

Reactive Ion Beam Etching (RIBE) of MTJ Cell using H₂/NH₃ plasma for Magnetic Random Access Memories

김두산,김예은,장윤종,김인호,김형용,채명관,염근영 한국진공학회 2021 한국진공학회 학술발표회초록집 Vol.2021 No.2

MRAM을 구동하기 위해 Magnetic Tunnel Junction (MTJ)층이 사용되며, 일반적으로 MTJ 층은 fixed layer, free layer, barrier layer로 구성된다. MTJ의 자성층 재료로써 CoFeB 및 CoPt가 일반적으로 사용되고 있으며, 이러한 MTJ cell 식각을 위해서 halogen-based RIE가 이용된다. 그러나, halogen 기체와 자성재료가 반응하여 halogen compound를 형성할 경우, 이는 non-volatile한 화합물로써 화학적 손상을 주게 되며, 식각 과정에서 패턴의 측벽에 다시 재 증착 되는 문제 등으로 인해 쉽게 제거되지 않는다. 본 연구에서는 이러한 문제를 해결하기 위해 H₂/NH₃ 가스조합을 이용한 RIBE를 통해 CoFeB 박막의 식각 특성을 확인하였다.

MLC STT-MRAM Cache을 위한 Dead Block 탐지 기반의 적응형 쓰기 기법

홍석인(Seokin Hong) 한국컴퓨터정보학회 2020 韓國컴퓨터情報學會論文誌 Vol.25 No.3

본 논문에서는 MLC STT-MRAM 캐시 메모리의 쓰기 동작 성능을 향상시킬 수 있는 효율적인 쓰기 기법을 제안한다. 제안하는 기법의 핵심 아이디어는 MLC STT-MRAM에 저장된 캐시 블록이 데드 블록 (Dead block)일 경우 쓰기 동작을 빠르게 수행하는 것이다. 이러한 빠른 쓰기 동작은 MLC STT-MRAM에 저장된 캐시 블록을 제거할 수 있지만, 제거된 블록이 앞으로 사용되지 않는 데드 블록일 경우에는 시스템 성능에 미치는 영향이 매우 작다. 메모리 시뮬레이터를 사용한 실험 평가를 통해 본 논문에서 제안하는 쓰기 기법이 MLC STT-MRAM 캐시의 성능을 평균 17% 향상시킬 수 있음을 보인다. In this paper, we propose an efficient adaptive write scheme that improves the performance of write operation in MLC STT-MRAM caches. The key idea of the proposed scheme is to perform the write operation fast if the target MLC STT-MRAM cells contain a dead block. Even if the fast write operation on the MLC STT-MRAM evicts a cache block from the MLC STT-MRAM cells, its performance impact is low if the evicted block is a dead block which is not used in the future. Through experimental evaluation with a memory simulator, we show that the proposed adaptive write scheme improves the performance of the MLC STT-MRAM caches by 17% on average.

MRAM Technology for High Density Memory Application

Kim, Chang-Shuk,Jang, In-Woo,Lee, Kye-Nam,Lee, Seaung-Suk,Park, Sung-Hyung,Park, Gun-Sook,Ban, Geun-Do,Park, Young-Jin The Institute of Electronics and Information Engin 2002 Journal of semiconductor technology and science Vol.2 No.3

MRAM(magnetic random access memory) is a promising candidate for a universal memory with non-volatile, fast operation speed and low power consumption. The simplest architecture of MRAM cell is a combination of MTJ(magnetic tunnel junction) as a data storage part and MOS transistor as a data selection part. This article will review the general development status of MRAM and discuss the issues. The key issues of MRAM technology as a future memory candidate are resistance control and low current operation for small enough device size. Switching issues are controllable with a choice of appropriate shape and fine patterning process. The control of fabrication is rather important to realize an actual memory device for MRAM technology.

A Comparative Study of MRAM Sensing Circuits in 65nm Technology

Jisu Kim,Jee-hwan Song,Kyung Ho Ryu,Seung H. Kang,Seong-Ook Jung 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7

Magnetic random access memory (MRAM) offers a compelling combination of attributes as a nonvolatile memory in performance, power, endurance, and integratability into logic devices. As the process technology continues to scale down to the nano-scale regime, however, the design of MRAM circuits has become challenging mainly due to the reduction in supply voltage and the increase in process variation. In this paper, we compare and analyze the representative MRAM sensing circuits based on a 65nm technology. We then suggest the most effective MRAM sensing circuit among representative cases considering sensing margin, delay, power, and area.