저전력 BLE/ZigBee IoT MCU 용 RF transciever 설계 연구

정지학,김응주 한국지식정보기술학회 2020 한국지식정보기술학회 논문지 Vol.15 No.1

Recently, the demand of BLE/ZigBee IoT MCU is highly increased for low power sensor network realization. In this paper, a low power and low cost BLE/ZigBee RF transceiver is studied with careful review of Bluetooth 5.0 core specification for BLE and IEEE 802.15.4 ZigBee specification. For the receiver side, a low-IF architecture with digital filtering and high ADC dynamic range is used to eliminate the analog filter to achieve both of small size and low power consumption simultaneously. Thanks to the inherent characteristics of a low-IF receiver, the proposed architecture also has the merits of high performance because of no signal loss due to DC offset removal filter and no flicker noise. For the transmitter side, a direct frequency modulation based on two point modulation and gain and phase mismatch calibration is proposed also for low power consumption. Moreover, 5bit binary-weighted inverse class-F power amplifier is proposed because the inverse class-F power amplifier shows greatly improved power efficiency even better than that of the class-F power amplifier. The 5bit binary-weighting is used for maximum transmit output power control as well as transmitter ramping for on-to-off and off-to-on transition. To meet FCC spurious emission regulation, on-chip and off-chip LC filtering and LO duty ratio control to suppress 3rd harmonic and 2nd harmonic, respectively. Finally, this paper presents the power architecture, which can support battery operation and solid power supply operation for best power efficiency and BOM cost optimization.

Design and Simulation of Novel 10-T Subtraction Logic for ALU Design Using GDI Technique

Haramardeep Singh,Harmeet Kaur 보안공학연구지원센터 2015 International Journal of Hybrid Information Techno Vol.8 No.7

Design based upon CMOS logic are becoming increasingly attractive for many applications under electronic gadgets, but with increasing demand of small and portable devices, new techniques for low power are emerging. This paper focus on the design of subtarction logic for ALU sub-module in microprocessor design. Set of four different 10-T subtraction logic using Gate Diffusion Index(a new technique for low power design) has been designed using 180nm technology using Cadence Virtuoso and simulation are performed . Complete verification for performance of proposed subtraction logic is carried and circuit with least power and delay has been selected for the ALU design of the microprocessor. Layout design for the best optimum ciruit is designed using Layout XL and area of 17.28 X 11.135 um2 is calculated.

A Novel Low Power Design of ALU Using Ad Hoc Techniques

Ankur Agarwa,A. S. Pandya,YoungUhg Lho 한국지능시스템학회 2005 INTERNATIONAL JOURNAL of FUZZY LOGIC and INTELLIGE Vol.5 No.2

This paper presents the comparison and performance analysis for CPL and CMOS based designs. We have developed the Verilog-HDL codes for the proposed designs and simulated them using ModelSim for verifying the logical correctness and the timing properties of the proposed designs. The proposed designs are then analyzed at the layout level using LASI. The layouts of the proposed designs are simulated in Winspice for timing and power characteristics. The result shows that the new circuits presented consistently consume less power than the conventional design of the same circuits. It can also be seen that these circuits have the lesser propagation delay and thus higher speed than the conventional designs.

Implementation of low power adder design and analysis based on power reduction technique

Elsevier 2008 Microelectronics Journal Vol.39 No.12

This paper presents improved design of low power adder and analysis based on power reduction technique. Using example of adder and multiplier, low leakage power CMOS digital circuit is verified by respective benchmark suite for each example and compared with conventional design of adder and multiplier. Using various supply voltages and fault coverage as parameters, reduction in power was measured. Simulation result and validation by example foresee implementation of proposed design as an essential part of high performance circuit design. The proposed technique offer power reduction up to 20.2% and fault coverage of 99.65%.

파워 스위치 구조를 결합한 비동기 회로 설계

김경기(Kyung Ki Kim) 한국산업정보학회 2016 한국산업정보학회논문지 Vol.21 No.1

본 논문은 동기회로에서 누설 전류를 줄이기 위해서 사용되는 파워 스위치 구조를 결합한 새로운 구조의 저전력 비동기 회로 설계 방법을 제안하고자 한다. Static 방식, Semi-static 방식과 같은 기존의 지연 무관방식의 비동기 방식과 비교해서 다소 속도의 손해는 있지만, 파워 스위치에 의해서 데이터가 없는 상태에서는 누설 전력을 줄일 수 있고, 전체 사이즈가 작아짐으로써 데이터가 입력되는 순간의 스위칭 전력도 줄일 수 있는 장점이 있다. 따라서, 제안된 방법은 속도보다 저전력을 기본으로 하는 사물인터넷시스템에서 요구되는 전전력 설계 방법이 될 것이다. 본 논문에서는 새로운 방식의 비동기 회로를 사용하여 4x4곱셈기를 0.11㎛ 공정으로 설계하고, 기존의 비동기 방식의 곱셈기와 스피드, 누설 전류, 스위칭 파워, 회로 크기 등을 비교하였다. This paper proposes an ultra-low power design methodology for asynchronous circuits which combines with power switch structure used for reducing leakage current in the synchronous circuits. Compared to existing delay-insensitive asynchronous circuits such as static NCL and semi-static NCL, the proposed methodology provides the leakage power reduction in the NULL mode due to the high Vth of the power switches and the switching power reduction at the switching moment due to the smaller area even though it has a reasonable speed penalty. Therefore, it will become a low power design methodology required for IoT system design placing more value on power than speed. In this paper, the proposed methodology has been evaluated by a 4x4 multiplier designed using 0.11 ㎛ CMOS technology, and the simulation results have been compared to the conventional asynchronous circuits in terms of circuit delay, area, switching power and leakage power.

패스 트랜지스터 논리를 이용한 저 전력 16×16 비트 변형된 부스 곱셈기 설계

홍성표,김정범 강원대학교 정보통신연구소 2009 정보통신논문지 Vol.13 No.-

This paper describes a low-power 16x16-bit modified Booth multiplier. To achieve low-power performance, the multiplier is designed with pass-transistor logic circuits. The pass-transistor logic circuits have excellent low-power characteristics compared with conventional CMOS logic circuits. The partial-product generator and 2's complement addition circuitry are designed with the pass-transistor logic circuits. The designed multiplier is achieved to reduce the power consumption by 22.8% and the power-delay-product by 17.5% compared with the conventional CMOS logic circuit. This circuit is designed with Hynix 0.25 itm standard CMOS process. The validity and effectiveness are verified through the HSPICE simulation.

저전력 휴대용 임베디드 시스템 설계 및 구현

이정환(Jung-Hwan Lee),김명준(Myung-Jung Kim) 한국정보과학회 2007 정보과학회 컴퓨팅의 실제 논문지 Vol.13 No.7

최근 휴대용 임베디드(Embedded) 시스템들은 크기는 작아지나 사용자들의 요구를 만족시키기 위해서 여러 가지 복합적인 기능을 내장하고 있다. 복합적인 기능 수행을 하기 위해서는 처리 능력이 뛰어난 프로세서들을 사용해야만 하고 시스템의 크기를 줄이기 위해서 적은 용량의 배터리를 사용하는 것이 일반적이다. 그러므로 시스템을 한번 충전한 후에 사용할 수 있는 배터리 사용 시간(Battery Life Time)은 중요한 문제로 대두되고 있다. 시스템의 배터리 사용 시간을 늘리기 위해서는 효율적인 전원 설계, 기능 수행에 따른 전력 관리 그리고 프로세서의 전압과 프로세서 클럭(Clock)의 주파수를 최적화하는 것이 가장 중요하다. 이를 위해서 본 논문에서는 전력 효율을 예측하여 시스템의 전체적인 전력 효율을 최적화하는 전원 구성을 하였으며 각 기능에 따른 전력 관리를 위해서 음악 파일 재생과 동영상 파일 재생을 위한 마이크로 프로세서를 사용하고 디지털 멀티미디어 방송(Digital Multimedia Broadcasting) 시청을 위한 별도의 마이크로 프로세서를 사용함으로써 음악 재생과 동영상 재생 시에는 디지털 멀티미디어 방송시청을 위한 마이크로 프로세서에 전원 공급을 차단함으로써 전력 관리를 최적화한다. 마지막으로 시스템에서 사용되는 프로세서들의 전력 관리를 위해 가변 전압 주파수 스케일링(Dynamic Voltage and Frequency Scaling)을 적용하여 프로세서들 또한 최적화하고 실제 구현된 시스템에 실험 결과들을 통하여 감소된 소비 전력의 결과를 보여준다. Portable embedded systems have recently become smaller in size and offer a variety of functions for users. These systems require high performance processors to handle the many functions and also a small battery to fit inside the system. However, due to its size, the battery life has become a major issue. It is important to have both efficient power design and management for each function, while optimizing processor voltage and clock frequency in order to extend the battery life of the system. In this paper, we calculated the efficiency of power in optimizing power rail. This system has two microprocessors. One is used to play music and movie files while the other is for DMB. In order to reduce power consumption, the DMB microprocessor is turned of while music or videos are played. Lastly, DVFS is applied to the processor in the system to reduce power consumption. Experimental results of the implemented system have resulted in reduced power consumption.

Design and Simulation of Novel 10-T Subtraction logic for ALU design using GDI Technique

Haramardeep Singh,Harmeet Kaur 보안공학연구지원센터 2015 International Journal of Hybrid Information Techno Vol.8 No.10

Design based upon CMOS logic are becoming increasingly attractive for many applications under electronic gadgets, but with increasing demand of small and portable devices, new techniques for low power are emerging. This paper focus on the design of subtarction logic for ALU sub-module in microprocessor design. Set of four different 10 -T subtraction logic using Gate Diffusion Index(a new technique for low power design) has been designed using 180nm technology using Cadence Virtuoso and simulation are performed . Complete verification for performance of proposed subtraction logic is carried and circuit with least power and delay has been selected for the ALU design of the microprocessor. Layout design for the best optimum ciruit is designed using Layout XL and area of 17.28 X 11.135 m2 is calculated.

Design and Simulation of Novel 10-T Subtraction Logic for ALU Design using GDI Technique

Haramardeep Singh,Harmeet Kaur 보안공학연구지원센터 2016 International Journal of Hybrid Information Techno Vol.9 No.2

Design based upon CMOS logic are becoming increasingly attractive for many applications under electronic gadgets, but with increasing demand of small and portable devices, new techniques for low power are emerging. This paper focus on the design of subtarction logic for ALU sub-module in microprocessor design. Set of four different 10-T subtraction logic using Gate Diffusion Index(a new technique for low power design) has been designed using 180nm technology using Cadence Virtuoso and simulation are performed . Complete verification for performance of proposed subtraction logic is carried and circuit with least power and delay has been selected for the ALU design of the microprocessor. Layout design for the best optimum ciruit is designed using Layout XL and area of 17.28 X 11.135 μm2 is calculated.

A Novel Low Power Design of ALU Using Ad Hoc Techniques

Agarwa, Ankur,Pandya, A.S.,Lho, Young-Uhg Korean Institute of Intelligent Systems 2005 INTERNATIONAL JOURNAL of FUZZY LOGIC and INTELLIGE Vol.5 No.2

This paper presents the comparison and performance analysis for CPL and CMOS based designs. We have developed the Verilog-HDL codes for the proposed designs and simulated them using ModelSim for verifying the logical correctness and the timing properties of the proposed designs. The proposed designs are then analyzed at the layout level using LASI. The layouts of the proposed designs are simulated in Winspice for timing and power characteristics. The result shows that the new circuits presented consistently consume less power than the conventional design of the same circuits. It can also be seen that these circuits have the lesser propagation delay and thus higher speed than the conventional designs.