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Evenly transferred single-layered graphene membrane assisted by strong substrate adhesion
Park, Seongjae,Kim, Hoijoon,Seol, Daehee,Park, Taejin,Leem, Mirine,Ha, Hyunwoo,An, Hyesung,You Kim, Hyun,Jeong, Seong-Jun,Park, Seongjun,Kim, Hyoungsub,Kim, Yunseok IOP 2017 Nanotechnology Vol.28 No.14
<P>We explored the transfer of a single-layered graphene membrane assisted by substrate adhesion. A relatively larger adhesion force was measured on the SiO<SUB>2</SUB> substrate compared with its van der Waals contribution, which is expected to result from the additional contribution of the chemical bonding force. Density functional theory calculations verified that the strong adhesion force was indeed accompanied by chemical bonding. The transfer of single-layered graphene and subsequent deposition of the dielectric layer were best performed on the SiO<SUB>2</SUB> substrate exhibiting a larger adhesion force. This study suggests the selection and/or modification of the underlying substrate for proper transfer of graphene as well as other 2D materials similar to graphene.</P>
A Gated Twin-Bit (GTB) Nonvolatile Memory Device and Its Fabrication Method
Seongjae Cho,Il Han Park,Yoon Kim,Se Hwan Park,Jong Duk Lee,Hyungcheol Shin,Byung-Gook Park IEEE 2009 IEEE TRANSACTIONS ON NANOTECHNOLOGY Vol.8 No.5
<P>In this study, a nonvolatile memory (NVM) device of novel structure in three-dimension is introduced and validated. It is based on a pillar structure where two memory nodes commonly reside. The storage nodes are controlled by a single control gate so that spaces between silicon pillars can be reduced, in which additional gates called cutoff gates realize perfect operations. Gated twin-bit (GTB) NVM device is considered as the ultimate form of 3-D NVM device based on double-gate structure in a sense that the use of common gate makes maximal integration possible. The operation schemes and fabrication method of the GTB NVM device are also introduced.</P>
Recessed Channel Dual Gate Single Electron Transistors (RCDG-SETs) for Room Temperature Operation
PARK, Sang Hyuk,KANG, Sangwoo,CHO, Seongjae,LEE, Dong-Seup,LEE, Jung Han,YANG, Hong-Seon,KANG, Kwon-Chil,LEE, Joung-Eob,LEE, Jong Duk,PARK, Byung-Gook The Institute of Electronics, Information and Comm 2009 IEICE transactions on electronics Vol.92 No.5
<P>A Recessed-Channel Dual-Gate Single Electron Transistor (RCDG-SET) which has the possibility of room temperature operation is proposed. Side gates of a RCDG-SET form electrical tunneling barriers around a recessed channel, which is newly introduced. Not only gate but also a recessed channel is self aligned to source and drain. Characteristics of a RCDG-SET are compared with those of previous DG-SETs through device simulation (SILVACO). Due to a recessed channel and a self aligned structure, MOSFET current which causes low Peak-to-Valley Current Ratio (PVCR) is suppressed. This property of a RCDG-SET is expected to contribute for room temperature operation.</P>
Park, Il Han,Kim, Tae Hun,Cho, Seongjae,Lee, Jung Hoon,Lee, Jong Duk,Park, Byung-Gook IEEE 2006 IEEE TRANSACTIONS ON NANOTECHNOLOGY Vol.5 No.3
A novel array architecture [depletion-enhanced body-isolation (DEBI)] has been proposed for NAND-type flash memories, and its memory characteristics are investigated in detail by device simulations. Having the shallow junctions on the thin active area, the proposed array architecture achieves high device performances with a fully depleted silicon-on-insulator (FDSOI) structure and enables stable erase operation without any problems based on an SOI structure. In particular, during the program operation, the DEBI architecture exhibited excellent self-boost efficiency originating from the isolated body. This can reduce the program disturbance effectively and can lower the V<SUB>pass</SUB> voltages.
GCMA: Guaranteed Contiguous Memory Allocator
Park, SeongJae,Kim, Minchan,Yeom, Heon Y. IEEE 2019 IEEE Transactions on Computers Vol.68 No.3
<P>The importance of physically contiguous memory has increased in modern computing environments, including both low- and high-end systems. Existing physically contiguous memory allocators generally have critical limitations. For example, the most commonly adopted solution, the memory reservation technique, wastes a significant amount of memory space. Scatter/Gather direct memory access (DMA) and input-output memory management units (IOMMUs) avoid this problem by utilizing additional hardware for address space virtualization. However, additional hardware means an increase in costs and power consumption, which is especially disadvantageous for small systems and they do not provide real contiguous memory. Linux Contiguous Memory Allocator (CMA) aims to provide both contiguous memory allocation and to maximize memory utilization based on page migration, but they suffer from unpredictably long latency and a high probability of allocation failure. Therefore, we introduce a new solution to this problem, the guaranteed contiguous memory allocator (GCMA). This guarantees efficient memory space utilization, short latency, and successful allocation. The GCMA uses a reservation scheme and increases memory utilization by sharing the memory with immediately discardable data. Our evaluation of a GCMA on a Raspberry Pi 2 finds a latency that is 15-130 times lower compared to a CMA, and a latency that is up to 10 times lower when taking a photo. Using a large working set in a memory-fragmented high-end system, the GCMA is able to produce a 2.27x speedup.</P>
Seongjae Cho,Il Han Park,Younghwan Son,Jong Duk Lee,Hyungcheol Shin,Byung-Gook Park 대한전자공학회 2008 ICEIC:International Conference on Electronics, Inf Vol.1 No.1
Many types of flash memory devices are fabricated on silicon-on-insulator (SOI) substrate for higher program efficiency nowadays [1]. However, it is relatively difficult to predict the program efficiency of NOR type flash memory device using channel hot electron injection (CHEI) mechanism accurately since metal-oxide-semiconductor (MOSFET) on SOI has a floating body. For this reason, the property of SOI memory device is quite different from that of bulk silicon device where the program efficiency can be easily controlled by the back substrate bias [2]. In spite of the difficulty in the enhancement of program efficiency assisted by substrate biasing, there are factors enabling the enhancement of efficiency. In this work, the dependence of program efficiency for SOI memory device with 200 ㎚ channel length on implementation conditions such as SOI thickness and channel doping concentration was investigated with the aid of numerical device simulation [3].
Seongjae Cho,Il Han Park,Tae Hun Kim,Jung Hoon Lee,Jong Duk Lee,Hyungcheol Shin,Byung-Gook Park 대한전자공학회 2005 Journal of semiconductor technology and science Vol.5 No.3
Recently, a novel multi-bit nonvolatile memory based on double gate (DG) MOSFET is proposed to overcome the short channel effects and to increase the memory density. We need more complex voltage schemes for DG MOSFET devices. In view of peripheral circuits driving memory cells, one should consider various voltage sources used for several operations. It is one of the key issues to minimize the number of voltage sources. This criterion needs more caution in considering a DG nonvolatile memory cell that inevitably requires more number of events for voltage sources. Therefore figuring out the permissible range of operating bias should be preceded for reliable operation. We found that reliable operation largely depends on the depletion conditions of the silicon channel according to charge amount stored in the floating gates and the negative control gate voltages applied for read operation. We used Silvaco Atlas, a 2-D numerical simulation tool as the device simulator.
Seongjae Cho,Chen, R.,Sukmo Koo,Shambat, G.,Lin, H.,Namkyoo Park,Vuckovic, J.,Kamins, T. I.,Byung-Gook Park,Harris, James S. IEEE 2011 IEEE photonics technology letters Vol.23 No.20
<P>In this work, a whispering gallery mode (WGM) microdisk resonator based on Ge<SUB>1-</SUB><I>x</I>Sn<I>x</I> grown by molecular beam epitaxy (MBE) was fabricated and characterized. Various process conditions and different Sn contents (4% and 1%) were explored to confirm the feasibility of Ge<SUB>1-</SUB><I>x</I>Sn<I>x</I> for microcavity device operation. Optical modes with wavelengths in the infrared (IR) range beyond 1550 nm were successfully confined in the devices fabricated with different diameters, and free-spectral ranges (FSRs) near 20 nm were obtained.</P>