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Novel Architecture of EER Transmitter with Class-E Amplifier
Tadashi Suetsugu,Xiuqin Wei,Shotaro Kuga 전력전자학회 2015 ICPE(ISPE)논문집 Vol.2015 No.6
This paper presents a novel architecture of the envelope elimination and restoration (EER) transmitter with the class-E amplifier. A design example is also given along with the PSpice-simuIation results. In the proposed architecture, a MOSFET is added and connected to the dc-feed inductance of the class-E amplifier in parallel, basing on the conventional Envelope Pulse Width Modulation (EPWM)-EER architecture. Therefore, it is possible to obtain no transient-attenuation performance, low surge voltage, and fast rising-time response by applying the proposed architecture. In other words, the proposed architecture can realize all performance of the improved EPWM-EER architecture, i.e., the Psuedo-EPWM or Preceding EPWM (pEPWM), but without carrying out the process of trial and error, which is required in the pEPWM architecture. The PSpice-simulation results show the effectiveness and validity of the proposed architecture.
Active Voltage Clamping of Class E Amplifier
Tadashi Suetsugu 전력전자학회 2011 ICPE(ISPE)논문집 Vol.2011 No.5
In this paper, a lossless voltage clamp method with an auxiliary switch is proposed as a remedy for the high peak switch voltage of the class E amplifier. In the proposed method, the auxiliary switch is operated with synchronized drive circuit. Output power can be regulated by adjusting phase of auxiliary switch.
Takeshi Yasukouchi,Tadashi Suetsugu 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
This paper analyzes maximum output power of class E amplifier with arbitrary transistor. It is important to estimate maximum output power of class E amplifier when a specification of transistor is given. In this paper, values of circuit parameters that gives maximum output power for given operating frequency, dc supply voltage, and output capacitance of the transistor are calculated. This paper presents scheme to calculate circuit parameters that maximum output power in this condition. Finally, some example calculations are shown when this scheme was applied to some actual power MOSFET transistors.
Applying User Monitoring for Display Power Management
Vasily G. Moshnyaga,Koji Hasimoto,Tadashi Suetsugu 제어로봇시스템학회 2009 제어로봇시스템학회 국제학술대회 논문집 Vol.2009 No.8
This paper discusses a new technology for reducing energy of computer display. Unlike existing power management schemes, which link the display operation to a key press or movement of the mouse, we use vision sensor to bind the display power state to the actual user"s attention. The technology tracks the user"s eyes, keeping the display active only if the user looks at the screen. Otherwise it dims the display down or even switches it off to save energy. We implemented the technology in hardware and present the results of their experimental evaluation.