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A Parallel Approach to Fault Simulation on the Connection Machine
Park, Taegeun 가톨릭대학교 자연과학연구소 1999 자연과학논문집 Vol.20 No.-
본 연구에서는 Connection Machine을 이용하여 PPSFP(Parallel Pattern Single Fault Propagation) 형태의 데이터 레벨 고속 병렬화 알고리즘을 구현하였다. 실험에 이용된 입력 패턴을 얻기 위하여 LFSR(Linear Feedback Shift Register)의 Cellular Automata를 이용하여 Pseudo-Random Pattern Generator를 구현하였다. 병렬 Fault Simulator의 출력은 주어진 회로의 각 도선에서 가능한 모든 sa0(stuck-at-0) and sa1(stuck-at-1) 오류를 검색하기 위한 입력 패턴을 찾아 테이블을 완성한다. 또한 그에 필요한 수행 시간과 fault coverage, 각 오류 형태의 출력 패턴을 제공한다. 알고리즘은 C^(*)와 PARIS 언어를 복합적으로 이용하여 구현되었다. A fast algorithm for the fault simulation using data level parallelism is implemented on the Connection Machine. The algorithm employed is the PPSFP(Parallel Pattern Single Fault Propagation) type. The input of the algorithm is the PI(Primary Input) test patterns obtained from a cellular automata pseudo-random pattern generator. The output of this system is a fault simulation table that describes the necessary test input patterns to detect both sa0(stuck-at-0) and sa1 (stuck-at-1) faults of the particular link in a given circuit. The output also includes fault-free, sa0, and sa1 output pattern, fault coverage and fault simulation time. The algorithm has been implemented using a combination of C^(*) and PARIS environment.
파이프라인 구조를 이용한 MAC(Multiply-and-Accumulate) 모듈 구현
박태근 가톨릭대학교 자연과학연구소 2000 자연과학논문집 Vol.21 No.-
본 연구에서는 통신용 알고리즘이나 다차원 신호처리 등의 응용분야에 가장 기본적으로 사용되는 복소수 누적승산(Multiply-and-Accumulate) 알고리즘을 배열 곱셈기(BAM)와 캐리 예측 덧셈기(CLA)를 사용하여 구현하였다. 고속 연산처리를 위하여 3-스테이지 파이프라인 구조를 적용하였다. 제안된 MAC 모듈 구조는 VHDL 언어로 모델링 되었고 그의 기능은 Xilinx FPGA로써 구현, 검증하였다. 파이프라인 스테이지를 셋으로 나눔으로써 좀더 효율인 연산을 하여 전체 처리 속도가 개선되었다. In this research, we proposed a pipelined MAC(Multiply-and-Accumulate) Module which is a basic arithmetic algorithm used in the various application areas, such as digital communication and digital signal processing. The proposed pipelined MAC module consists of BAM(Braun Array Multiplier) and CLA(Carry Lookahead Adders). We designed the MAC module with 3-stage pipeline for the better performance. The proposed architecture is modeled and simulated using VHDL language and verified by the Xilinx FPGA design tool kit. The result shows us the correct execution and the better performance due to the pipeline.
Design of the (248,216) Reed-Solomon decoder with erasure correction for Blu-ray disc
IEEE 2005 IEEE transactions on consumer electronics Vol.51 No.3
This paper presents an efficient VLSI architecture of the (248, 216) Reed-Solomon decoder with erasure correction capability for Blu-ray disc (BD). The proposed architecture is designed with four-stage pipelines: the syndrome and erasure location polynomials calculation, the errata location polynomial calculation, the errata evaluation polynomial calculation, and the Chien search and errata value evaluation. Each stage is carefully balanced to maximize the throughput of the pipeline for BD applications. To solve the key equation, the Berlekamp-Massey algorithm is transformed into a symbol-serial structure and the fully utilized VLSI architecture, maintaining the maximum decoding performance, is proposed. Therefore, the proposed architecture maximizes the throughputs requiring less hardware resources. The gate counts for the proposed RS decoder is 74K using the Hynix 0.35 μm standard cell library and the maximum throughput is 700 Mbps at 100 MHz, which is fast enough for 16× BD applications.
No-Reference Sharpness Assessment of Camera-Shaken Images by Analysis of Spectral Structure
Taegeun Oh,Jincheol Park,Seshadrinathan, Kalpana,Sanghoon Lee,Bovik, Alan Conrad IEEE 2014 IEEE TRANSACTIONS ON IMAGE PROCESSING - Vol.23 No.12
<P>The tremendous explosion of image-, video-, and audio-enabled mobile devices, such as tablets and smart-phones in recent years, has led to an associated dramatic increase in the volume of captured and distributed multimedia content. In particular, the number of digital photographs being captured annually is approaching 100 billion in just the U.S. These pictures are increasingly being acquired by inexperienced, casual users under highly diverse conditions leading to a plethora of distortions, including blur induced by camera shake. In order to be able to automatically detect, correct, or cull images impaired by shake-induced blur, it is necessary to develop distortion models specific to and suitable for assessing the sharpness of camera-shaken images. Toward this goal, we have developed a no-reference framework for automatically predicting the perceptual quality of camera-shaken images based on their spectral statistics. Two kinds of features are defined that capture blur induced by camera shake. One is a directional feature, which measures the variation of the image spectrum across orientations. The second feature captures the shape, area, and orientation of the spectral contours of camera shaken images. We demonstrate the performance of an algorithm derived from these features on new and existing databases of images distorted by camera shake.</P>