http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
Electrical Test for Open Defects in CMOS ICs by Injected Charge
Daisuke Suga,Hiroyuki Yotsuyanagi,Masaki Hashizume 대한전자공학회 2015 ITC-CSCC :International Technical Conference on Ci Vol.2015 No.6
In this paper, an electrical test method is proposed for open defects in CMOS ICs. The test method is based on amount of charge injected from a power supply voltage source. Also, it is examined by Spice simulation whether an open defect in an inverter chain circuit can be detected by the test method. The simulation results show us that an open defect can be detected by the test method.
Feasibility of IDDQ Tests for Shorts in Deep Submicron ICs
Isao Tsukimoto,Hiroyuki Yotsuyanagi,Masaki Hashizume 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
Quiescent supply current(IDDQ) in deep submicron ICs is derived by circuit simulation and feasibility of IDDQ tests is examined for short defects in ICs fabricated with 0.18㎛ CMOS process. The results show that IDDQ of each gate depends on input logic values and that shorts can be detected by IDDQ testing if some process variations are small.
Open Lead Detection Based on Logical Change Caused by AC Voltage Signal Stimulus
Akira Ono,Masahiro Ichimiya,Hiroyuki Yotsuyanagi,Masao Takagi,Masaki Hashizume 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
In this paper, we propose a new test method for detecting an open lead which occurs when an IC is mounted on a printed circuit board. In the method, an open lead is detected by observing output logical change of an open lead detector. Since the test method is a vectorless test one, test generation and test input application are not needed. Testability of the test method is examined by some experiments. The results show that open leads of SSIs and LSIs will be detected by the method.
Current Testable Design of Resistor String DACs for Short Defects
Masaki Hashizume,Yutaka Hata,Hiroyuki Yotsuyanagi,Yukiya Miura 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
In this paper, we propose a DFT method for resistor string DACs that enables us to test them easily by supply current test method. The targeted defects are shorts in the DACs. It is shown by some experiments that all of the targeted defects in a DAC designed with the DFT method can be detected with a smaller number of test vectors.
Repair Circuit of TSVs in a 3D Stacked Memory IC
Yuki Ikiri,Masaki Hashizume,Hiroyuki Yotsuyanagi,Hiroshi Yokoyama,Tetsuo Tada,Shyue-Kung Lu 대한전자공학회 2015 ITC-CSCC :International Technical Conference on Ci Vol.2015 No.6
A repair circuit for TSVs (Through Silicon Vias) in a 3D stacked memory IC is proposed in this paper. The circuit is made of a switch circuit and a switch control circuit so as for a defective TSV to be connected to a defect-free TSV. The circuit is evaluated by Spice simulation. The results show us that a TSV is connected to a defect-free one with small area overhead and additional delay.
Fault Analysis of Interconnect Opens in 90nm CMOS ICs with Device Simulator
Masaki Hashizume,Yuichi Yamada,Hiroyuki Yotsuyanagi,Toshiyuki Tsutsumi,Koji Yamazaki,Yoshinobu Higami,Hiroshi Takahashi,Yuzo Takamatsu 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
In this paper, faulty effects of interconnect opens in logic ICs fabricated with a 90㎚ CMOS process are analyzed by device simulation. In the analysis, it is examined whether a logical error can be caused at an opened input signal line by logic signals of the neighboring signal lines. The simulation results suggest us that a logical error may occur at an interconnect surrounding by 8 interconnects if the interconnects are longer than 5㎛ and the width of an open defect is greater than 2.0㎚.
Current Testable Design of Resistor String DACs for Open Defects
Yutaka Hata,Masaki Hashizume,Hiroyuki Yotsuyanagi,Yukiya Miura 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
In this paper, a DFT method of resistor string digital-to-analog converters (DACs) is proposed so as to be tested fully by supply current testing. Targeted defects are opens in the DACs. Testability of opens in testable designed DACs is examined experimentally. The results show that all of the opens in an N-bits testable designed DAC will be detected with test vectors of about 2(N-1) by supply current testing.