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Design and Analysis of the DC–DC Converter With a Frequency Hopping Technique for EMI Reduction
Huynh, Hai Au,Han, Youngbong,Park, Sanghyeok,Hwang, Jisoo,Song, Eunseok,Kim, SoYoung IEEE 2018 IEEE transactions on components, packaging, and ma Vol.8 No.4
<P>As more circuit functions are integrated within a single die or small integrated package, the number of electromagnetic interference (EMI) problems caused by dc–dc converters is growing. In this paper, the dominant electromagnetic emission source on the dc–dc converter is identified by analyzing the power spectrum of the nodes. The noise scanner method is applied to a packaged single-chip prototype dc–dc converter. The results show that the dominant source of electromagnetic emission is the switching node of the converter, not the output node. The frequency hopping technique (FHT) is applied to the dc–dc converter to reduce the emission at the switching node, and its effectiveness is analyzed mathematically and experimentally. The mathematical model of FHTs is proposed to analyze its effectiveness in reducing EMI, and the optimal design using the FHT and dead-time control is fabricated with 0.18- <TEX>$\mu \text{m}$</TEX> CMOS technology. The measured power spectrum reduction by using the optimal FHT design and dead-time control at the switching node is 16 dB. The EMI reduction amount of the proposed design measured by the IC-stripline method is 12.6 dB at the fundamental switching frequency.</P>
Analysis of Power Transfer Efficiency of Standard Integrated Circuit Immunity Test Methods
Huynh, Hai Au,Lee, Hak-Tae,Nah, Wansoo,Kim, SoYoung Hindawi Limited 2015 International journal of antennas and propagation Vol.2015 No.-
<P>Direct power injection (DPI) and bulk current injection (BCI) methods are defined in IEC 62132-3 and IEC 62132-4 as the electromagnetic immunity test method of integrated circuits (IC). The forward power measured at the RF noise generator when the IC malfunctions is used as the measure of immunity level of the IC. However, the actual power that causes failure in ICs is different from forward power measured at the noise source. Power transfer efficiency is used as a measure of power loss of the noise injection path. In this paper, the power transfer efficiencies of DPI and BCI methods are derived and validated experimentally with immunity test setup of a clock divider IC. Power transfer efficiency varies significantly over the frequency range as a function of the test method used and the IC input impedance. For the frequency range of 15 kHz to 1 GHz, power transfer efficiency of the BCI test was constantly higher than that of the DPI test. In the DPI test, power transfer efficiency is particularly low in the lower test frequency range up to 10 MHz. When performing the IC immunity tests following the standards, these characteristics of the test methods need to be considered.</P>
EMC Qualification Methodology for Semicustom Digital Integrated Circuit Design
Huynh, Hai Au,Jo, Jeong-Min,Nah, Wansoo,Kim, SoYoung [Institute of Electrical and Electronics Engineers 2016 IEEE transactions on electromagnetic compatibility Vol.58 No.5
<P>In this paper, a simulation methodology and an electromagnetic compatibility qualification environment (EQE) are developed to verify the electromagnetic susceptibility of semicustom digital integrated circuits (IC) during the design phase. The immunity levels of the digital circuits are estimated by the functional failure and delay change caused by the external noise which is injected by bulk current injection (BCI) and direct power injection (DPI) methods. The model for the device under test (DUT), the standard cell parasitic model, and the equivalent circuit model of BCI and DPI test setup are developed for the IC immunity test. All test components and on-chip circuit models are linked by EQE to analyze the target DUT. The EQE can be applied to predict the immunity level of the design at the schematic level and postlayout level design. To validate the accuracy of the proposed simulation tool, EQE is applied to the design process of a clock divider (CKD) and a serial peripheral interface (SPI) circuits to verify their immunity levels. The CKD and SPI circuits are designed and fabricated using Magna 180 nm Complementary metal-oxide semiconductor (CMOS) technology. The immunity levels generated by the EQE are compared with the experimental measurement results. The comparison shows good agreement between simulation and measurement.</P>
Modeling of FinFET Parasitic Source/Drain Resistance With Polygonal Epitaxy
Kim, JungHun,Huynh, Hai Au,Kim, SoYoung Institute of Electrical and Electronics Engineers 2017 IEEE transactions on electron devices Vol.64 No.5
<P>In this paper, we introduce a new compact model of the parasitic resistance of a FinFET with a hexagonal-shaped raised source-drain (S/D) structure. In contrast to previousmodels that divided the extrinsic S/D region into three parts, we redefined the region boundaries and modeled them as a series connection of accumulation resistance, gradient resistance, bulk resistance, and contact resistance. The newly added bulk resistance-model accounts for the highly doped silicon region. We also significantly improved the contact resistance model to reflect the contact area and contact resistivity for better accuracy in the raised S/D region. We validated the accuracy of our model by varying the gate voltage, doping diffusion length, epitaxy silicon height, and contact resistivity, finding the model errors to be within 2% of the 3-D technology CAD device simulation results.</P>
Pinwheel Meander-Perforated Plane Structure for Mitigating Power/Ground Noise in System-in-Package
Han, Youngbong,Huynh, Hai Au,Kim, SoYoung IEEE 2018 IEEE transactions on components, packaging, and ma Vol.8 No.4
<P>In this paper, a small electromagnetic bandgap structure that is suitable to be integrated into system-in-package is designed. The proposed structure, which is named as pinwheel perforated plane (PMPP), consists of meander line, mushroom-type patch, and the extended ground structure that is called a pinwheel. The proposed structure comprises three layers: top, middle, and ground. Moreover, the size of the proposed unit cell is 2.44 mm <TEX>$\times \,\, 2.44$</TEX> mm. The 3-D electromagnetic simulation results reveal that the cascaded <TEX>$1\times 2$</TEX> PMPP structure generates a stopband frequency of 3.35–28.17 GHz at a suppression depth of −40 dB. The power/ground noise suppression effect is confirmed by dispersion analysis from 3-D electromagnetic solver eigenmodes. Signal and power co-simulations are also performed to validate its integrity.</P>
Trong Luan NGUYEN,Tran Gia Thanh LE,Bach Mai HUYNH,Thi Kieu Trang VO,Pham Hai Au HA 한국유통과학회 2021 The Journal of Asian Finance, Economics and Busine Vol.8 No.12
Gen Z is a special generation that was born with technology, converging the best development conditions making them an important part of the future development of Vietnam’s economy. Gen Z is an important part of the future development of Vietnam’s economy. The purpose of this study is to identify and measure the impact of various factors affecting the business intentions of Gen Z in Vietnam during the Covid pandemic. The study did not go into the details of entrepreneurship, instead focused on explaining the impact of factors such as risk-taking, market economic trends, influencers, confidence, and family business traditions on the business intentions of Gen Z. The study was carried out using quantitative and qualitative methods with 335 data points collected online via survey links. The methods used to test the scale such as Cronbach alpha, CFA, SEM are used to examine the correlation between factors affecting the business intention of Gen Z in Vietnam. The results showed that the business intention of Gen Z in Vietnam is positively correlated and significantly influenced by confidence and risk-taking. Furthermore, the study reveals a difference in entrepreneurship of Gen Z Vietnam based on gender and education level.