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Application of the EKV model to the DTMOS SOI transistor
Colinge, Jean-Pierre,Park, Jong-Tae The Institute of Electronics and Information Engin 2003 Journal of semiconductor technology and science Vol.3 No.4
The EKV model, a continuous model for the MOS transistor, has been adapted to both partially depleted SOI MOSFETs with grounded body (GBSOI) and dynamic threshold MOS (DTMOS) transistors. Adaptation is straightforward and helps to understand the physics of the DTMOS. Excellent agreement is found between the model and the measured characteristics of GBSOI and DTMOS devices
Growld Plane SOI MOSFET의 단채널 현상 개선
장성준,윤세레나,유종근,박종태,Jean-Pierre Colinge 대한전자공학회 2004 電子工學會論文誌-SD (Semiconductor and devices) Vol.41 No.4
매몰 산화층 밑의 실리콘 기판에 자기정렬 방법으로 ground plane 전극을 만든 SOI MOSFET의 단채널 현상과 Punchthrough 특성을 측정·분석하였다. 채널 길이가 $0.2{\mu}m$ 이하의 소자에서는 GP-SOI 소자가 FD-SOI 소자보다 채널 길이에 따른 문턱전압 저하 및 subthreshold swing이 작고 DIBL 현상이 크게 개선됨을 알 수 있었다. 기판전압에 따른 문턱전압 특성으로부터 GP-SOI 소자의 body factor가 FD-SOI 소자보다 큰 것을 알 수 있었다. 그리고 punchthrough 전압 특성으로부터 GP-SOI 소자의 punchthrough 전압이 FD-SOI 소자보다 큰 것을 알 수 있었다. This paper reports the measurement and analysis of the short channel effects and the punchthrough voltage of SOI-MOSFET with a self-aligned ground plane electrode in the silicon mechanical substrate underneath the buried oxide. When the channel length is reduced below 0.2${\mu}{\textrm}{m}$ it is observed that the threshold voltage roll-off and the subthreshold swing with channel length are reduced and DIBL is improved more significantly in GP-SOI devices than FD-SOI devices. It is also observed from the dependence of threshold voltage with substrate biases that the body factor is a higher in GP-SOI devices than FD-SOI devices. From the measurement results of punchthrough voltage, GP-SOI devices show the higher punchthrough voltages than FD-SOI devices
Ground Plane SOI MOSFET의 단채널 현상 개선
장성준,유종근,박종태,윤세레나,Jean-Pierre Colinge 대한전자공학회 2004 電子工學會論文誌-SD (Semiconductor and devices) Vol.41 No.04
This paper reports the measurement and analysis of the short channel effects and the punchthrough voltage of SOI-MOSFET with a self-aligned ground plane electrode in the silicon mechanical substrate underneath the buried oxide. When the channel length is reduced below 0.2um, it is observed that the threshold voltage roll-off and the subthreshold swing with channel length are reduced and DIBL is improved more significantly in GP-SOI devices than FD-SOI devices. It is also observed from the dependence of threshold voltage with substrate biases that the body factor is a higher in GP-SOI devices than FD-SOI devices. From the measurement results of punchthrough voltage, GP-SOI devices show the higher punchthrough voltages than FD-SOI devices 매몰 산화층 밑의 실리콘 기판에 자기정렬 방법으로 ground plane 전극을 만든 SOI MOSFET의 단채널 현상과 punchthrough 특성을 측정분석하였다. 채널 길이가 0.2μm 이하의 소자에서는 GP-SOI 소자가 FD-SOI 소자보다 채널 길이에 따른 문턱전압 저하 및 subthreshold swing이 작고 DIBL 현상이 크게 개선됨을 알 수 있었다. 기판전압에 따른 문턱전압 특성으로부터 GP-SOI 소자의 body factor가 FD-SOI 소자보다 큰 것을 알 수 있었다. 그리고 punchthrough 전압 특성으로부터 GP-SOI 소자의 punchthrough 전압이 FD-SOI 소자보다 큰 것을 알 수 있었다.
시뮬레이션에 의한 금속게이트 FD-SOI 와 MuGFET의 불소 이온 주입효과
이치우(Chi-Woo Lee),D. Lederer,A. Afzalian,Ran Yan,J.P. Colinge 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
Fluorine (F) implantation creates negative charges at the Si/SiO₂ interface in FDSOI transistors[1]. This paper describes simulation of the influence of F Implant on Threshold Voltage(Vth) for Metal Gate FDSOI and MuGFETs using FEMLAB<SUP>ⓡ</SUP> The origin of the large V th shift observed in planar FDSOI due to is the creation of negative charge states in the BOX by the F implant. F implant is a suitable approach for planar FDSOI SoC integration with single work function (WF) metal gate, but NOT for MuGFETs.
NBTI and hot-carrier effects in accumulation-mode Pi-gate pMOSFETs
Lee, C.W.,Ferain, I.,Afzalian, A.,Yan, R.,Dehdashti, N.,Razavi, P.,Colinge, J.P.,Park, J.T. Pergamon Press 2009 Microelectronics reliability Vol.49 No.9
Negative bias temperature instability (NBTI) and hot-carrier induced device degradation in accumulation-mode Pi-gate pMOSFETs have been studied for different fin widths ranging from 20 to 40nm. The NBTI induced device degradation is more significant in narrow devices. This result can be explained by enhanced diffusion of hydrogen at the corners in multiple-gate devices. Due to larger impact ionization, hot-carrier induced device degradation is more significant in wider devices. Finally, hot-carrier induced device degradation rate is highest under stress conditions where V<SUB>GS</SUB>=V<SUB>TH</SUB>.