http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
고속 파이프라인 A/D 변환기를 위한 연산 증폭기의 설계
손영찬,유상대,주리아 경북대학교 전자기술연구소 2001 電子技術硏究誌 Vol.22 No.2
In the design specifications of operational amplifiers which are used in high-speed pipeline A/D converters is analyzed, the technique to design using a design tool of operational amplifiers is proposed. The CMOS operational amplifier usable in 10-b 25-MHz pipelined A/D converters is designed. The operational amplifier designed using 1.2 ㎛ CMOS technology exhibits a do gain of 71 dB, a unity-gain frequency of 195 MHz, a phase margin of 57^*, a slew rate of 186 V/㎲, a output voltage swing of ± 1.1 V, and a power dissipation of 4 mW at 5 V supply voltage and 0.6 pF load. And applying to the S/H amplifier with a gain of 2 and a capacitive load of 0.5 pF the settling time of 14 ns for output voltage swing of 1 ± V satisfied the design specifications.
36-mW 10-bit 40-MS/s CMOS 파이프라인 A/D 변환기
손영찬,유상대,주리아 경북대학교 전자기술연구소 2000 電子技術硏究誌 Vol.21 No.1
In this paper, we describes a 10-bit 40 MS/s pipelined A/D converter with 0.8 um double-poly double-metal CMOS technology. It achieves low power static disssipation of 36㎽ at 5 V power supply. A 1.5 b/stage pipelined architecture in the designed A/D Converter is used to allow large correction range for comparator offset and perform the fast interstage signal processing. In order to design high resolution and low power pipelined A/D converter, the sample and hold amplifier is designed using op-amp sharing technique and dynamic comperator. In addition, fully-differential folded cascode op-amp with gain boosting is designed by using SAPICE. At 10 ㎒ input SNR is 56.7 dB. The DNL and INL exhibit ±0.6 LSB, +1/-0.75 LSB respectively.
기하 프로그래밍을 이용한 연산증폭기의 설계 자동화 기법
김정렬,손영찬,유상대,주리아 경북대학교 전자기술연구소 2000 電子技術硏究誌 Vol.21 No.1
We describe a method for optimized CMOS operational amplifier design. We observe that a wide variety of design objectives and constraints has polynomial functions of design variable. Thus, the amplifier design problem can be expressed as a form of optimization problem using geometric programming, which is very efficient global optimization methods which have been developed. In this paper, we use this method for a two-stage CMOS operational amplifier design. We compute globally optimal value, which satisfies objectives such as the power dissipation, crossover frequency, and open-loop gain.
손영찬,유상대,주홍일,주리아 경북대학교 전자기술연구소 1998 電子技術硏究誌 Vol.19 No.1
A CMOS RF bandpass amplifier which performs both functions of low-noise amplifier and bandpass filter is designed for the application of 900 ㎒ RF front-end in wireless receivers. The positive-feedback Q-enhancement technique is used to overcome the low gain and low Q factor of the bandpass amplifier. The Miller-capacitance tuning scheme compensates for the process variations of center frequency. The designed bandpass amplifier is simulated with HSPICE and fabricated using 0.8 ㎛ CMOS 2-poly 2-metal full custom process. Under 3 V supply voltage, results of simulation show that the CMOS bandpass amplifier provides the quality factor Q of 40 and the gain of 20 ㏈. The center-frequency tuning range is from 894 ㎒ to 906 ㎒ and power dissipation is about 72 ㎽.