머신러닝 컴파일러와 모듈로 스케쥴러에 관한 연구

조두산 한국산업융합학회 2024 한국산업융합학회 논문집 Vol.27 No.1

This study is on modulo scheduling algorithms for multicore processor in machine learning applications. Machine learning algorithms are designed to perform a large amount of operations such as vectors and matrices in order to quickly process large amounts of data stream. To support such large amounts of computations, processor architectures to support applications such as artificial intelligence, neural networks, and machine learning are designed in the form of parallel processing such as multicore. To effectively utilize these multi-core hardware resources, various compiler In study, techniques these being used and studied. this compiler among are techniques, we analyzed the modular scheduler, which is especially important in one core’s computation pipeline. This paper looked at and compared the iterative modular scheduler and the swing modular scheduler, which are the most widely used and studied. As a result, both schedulers provided similar performance results, and when measuring register pressure as an indicator, it was confirmed that the swing modulo scheduler provided slightly better performance. In this study, a technique that divides recurrence edge is proposed to improve the minimum initiation interval of the modulo schedulers.

A Case Study of a Navigator Optimization Process

조두산 한국인터넷방송통신학회 2017 Journal of Advanced Smart Convergence Vol.6 No.1

When mobile navigator device accesses data randomly, the cache memory performance is rapidly deteriorated due to low memory access locality. For instance, GPS (General Positioning System) of navigator program for automobiles or drones, that are currently in common use, uses data from 32 satellites and computes current position of a receiver. This computation of positioning is the major part of GPS which accounts more than 50% computation in the program. In this computation task, the satellite signals are received in real time and stored in buffer memories. At this task, since necessary data cannot be sequentially stored, the data is read and used at random. This data accessing patterns are generated randomly, thus, memory system performance is worse by low data locality. As a result, it is difficult to process data in real time due to low data localization. Improving the low memory access locality inherited on the algorithms of conventional communication applications requires a certain optimization technique to solve this problem. In this study, we try to do optimizations with data and memory to improve the locality problem. In experiment, we show that our case study can improve processing speed of core computation and improve our overall system performance by 14%.

Technology of the next generation low power memory system

조두산 한국인터넷방송통신학회 2018 International Journal of Internet, Broadcasting an Vol.10 No.4

As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation. These disadvantages can be solved using the compiler. The disadvantage of non-volatile memory is in write operations. Therefore, when the compiler decides the layout of the data, it is solved by optimizing the write operation to allocate a lot of data to the SRAM. This study provides insights into how these compiler and architectural designs can be developed.

스크래치패드 메모리를 위한 데이터 관리 기법 리뷰

조두산 국제문화기술진흥원 2023 The Journal of the Convergence on Culture Technolo Vol.9 No.1

Scratchpad memory is a software-controlled on-chip memory designed and used to mitigate the disadvantages of existing cache memories. Existing cache memories have TAG-related hardware control logic, so users cannot directly control cache misses, and their sizes are large and energy consumption is relatively high. Scratchpad memory has advantages in terms of size and energy consumption because it eliminates such hardware overhead, but there is a burden on software to manage data. In this study, data management techniques of scratchpad memory were classified and examined, and ways to maximize the advantages were discussed. 스크래치패드 메모리는 소프트웨어 제어 온칩 메모리로서 기존의 캐시 메모리의 단점을 완화할 수 있게 설계되어 이용되고 있다. 기존의 캐시 메모리는 태그 관련 하드웨어 제어 로직이 있어 캐시 미스를 사용자가 직접 제어할 수 없으며, 사이즈가 크고 에너지 소모량이 상대적으로 많다. 스크래치패드 메모리는 이러한 하드웨어 오버헤드를 제거하였기 때문에 사이즈, 에너지 소모량에서 장점이 있으나 데이터 관리를 소프트웨어가 해야하는 부담이 존재한다. 본 연구에서는 스크래치패드 메모리의 데이터 관리 기법들을 분류하여 살펴보고 그 장점을 극대화할 수 있는 방안에 대하여 논의하였다.

A Study on Efficient Use of Dual Data Memory Banks in Flight Control Computers

조두산 한국인터넷방송통신학회 2017 International Journal of Internet, Broadcasting an Vol.9 No.1

Over the past several decades, embedded system and flight control computer technologies have been evolved to meet the diverse needs of the mobile device market. Current embedded systems are at the heart of technologies that can take advantage of small-sized specialized hardware while still providing high-efficiency performance at low cost. One of these key technologies is multiple memory banks. For example, a dual memory bank can provide two times more memory bandwidth in the same memory space. This benefit take lower cost to provide the same bandwidth. However, there is still few software technologies to support the efficient use of multiple memory banks. In this study, we present a technique to efficiently exploit multiple memory banks by software support. Specifically, our technique use an interference graph to optimally allocate data to different memory banks by an optimizing compiler. As a result, the execution time can be improved upto 7% with the proposed technique.

이 달의 수필 : 갈라리 고담

조두산 대한지방행정공제회 1967 地方行政 Vol.16 No.167

특집 02 : 모바일 응용 서비스 ; Bluetooth Low Energy (BLE) 비콘 (Beacons)과 그 응용

조두산,김용주 한국정보처리학회 2015 정보처리학회지 Vol.22 No.6

머신러닝 기반 메모리 성능 개선 연구

조두산 국제문화기술진흥원 2021 The Journal of the Convergence on Culture Technolo Vol.7 No.1

이 연구는 사물인터넷, 클라우드 컴퓨팅 그리고 에지 컴퓨팅 등 많은 임베디드 시스템에서 성능 및 에너지 효 율을 높이고자 최적화하는 메모리 시스템에 초점을 맞추어 그 성능 개선 기법을 제안한다. 제안하는 기법은 최근 많 이 이용되고 있는 머신 러닝 알고리즘을 기반으로 메모리 시스템 성능을 도모한다. 머신 러닝 기법은 학습을 통하여 다양한 응용에 사용될 수 있는데, 메모리 시스템 성능 개선에서 사용되는 데이터의 분류 태스크에 적용될 수 있다. 정확도 높은 머신 러닝 기법 기반 데이터 분류는 데이터의 사용 패턴에 따라 데이터를 적절하게 배치할 수 있게 하 여 전체 시스템 성능 개선을 도모할 수 있게 한다. This study focuses on memory systems that are optimized to increase performance and energy efficiency in many embedded systems such as IoT, cloud computing, and edge computing, and proposes a performance improvement technique. The proposed technique improves memory system performance based on machine learning algorithms that are widely used in many applications. The machine learning technique can be used for various applications through supervised learning, and can be applied to a data classification task used in improving memory system performance. Data classification based on highly accurate machine learning techniques enables data to be appropriately arranged according to data usage patterns, thereby improving overall system performance.

차세대 저전력 멀티뱅크 메모리를 위한 컴파일러 최적화 기법

조두산,Cho, Doosan 한국인터넷방송통신학회 2021 한국인터넷방송통신학회 논문지 Vol.21 No.6

Various types of memory architectures have been developed, and various compiler optimization techniques have been studied to efficiently use them. In particular, since a memory is a major component that determines performance in mobile computing devices, various optimization techniques have been developed to support them. Recently, a lot of research on hybrid type memory architecture is being conducted, so various compiler techniques are being studied to support it. Existing compiler optimization techniques can be used to achieve the required minimum performance and constraint on low power according to market requirements. References for determining the low-power effect and the degree of performance improvement using these optimization techniques are not properly provided yet. This study was conducted to provide the experimental results of the existing compiler technique as a reference for the development of multibank memory architecture. 다양한 형태의 메모리 아키텍처가 개발되었고, 이를 효과적으로 사용하기 위한 여러 컴파일러 최적화 기법이 연구되었다. 특히, 모바일 컴퓨팅 디바이스에서 메모리는 성능을 결정하는 주요 컴포넌트이기 때문에 이를 지원하기 위한 다양한 최적화 기법들이 개발되었다. 최근에는 하이브리드 형태의 메모리 아키텍처에 대한 연구가 많이 진행되고 있기 때문에 이를 지원하기 위한 다양한 컴파일러 기법이 연구되고 있다. 시장의 요구조건에 맞추어 저전력에 대한 제약조건과 필요한 최소한의 성능을 달성하기 위하여 기존의 컴파일러 최적화 기법들이 사용될 수 있다. 이러한 최적화 기법들을 활용한 저전력 효과 및 성능 개선 정도를 파악하기 위한 레퍼런스가 제대로 제공되지 못하고 있는 실정이다. 본 연구는 기존의 컴파일러 기법에 대한 실험 결과를 멀티뱅크 메모리 아키텍처 개발의 레퍼런스로 제공하기 위하여 진행되었다.

단편소설 : 작크의 귀향

조두산 대한지방행정공제회 1969 地方行政 Vol.18 No.184