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Yun Seop Yu 대한전자공학회 2010 Journal of semiconductor technology and science Vol.10 No.2
We propose a semi-analytical current conduction model for depletion-mode n-type nanowire field-effect transistors (NWFETs) with top-gate structure. The NWFET model is based on an equivalent circuit consisting of two back-to-hack Schottky diodes for the metal-semiconductor (MS) contacts and the intrinsic top-gate NWFET. The intrinsic top-gate NWFET model is derived from the current conduction mechanisms due to bulk charges through the center neutral region as well as of accumulation charges through the surface accumulation region, based on the electrostatic method, and thus it includes all current conduction mechanisms of the NWFET operating at various top-gate bias conditions. Our previously developed Schottky diode model is used for the MS contacts. The newly developed model is integrated into ADS, in which the intrinsic part of the NWFET is developed by utilizing the Symbolically Defined Device (SDD) for an equation-based nonlinear model. The results simulated from the newly developed NWFET model reproduce considerably well the reported experimental results.
Compact Capacitance Model of L-Shape Tunnel Field-Effect Transistors for Circuit Simulation
Yu, Yun Seop,Najam, Faraz The Korea Institute of Information and Commucation 2021 Journal of information and communication convergen Vol.19 No.4
Although the compact capacitance model of point tunneling types of tunneling field-effect transistors (TFET) has been proposed, those of line tunneling types of TFETs have not been reported. In this study, a compact capacitance model of an L-shaped TFET (LTFET), a line tunneling type of TFET, is proposed using the previously developed surface potentials and current models of P- and L-type LTFETs. The Verilog-A LTFET model for simulation program with integrated circuit emphasis (SPICE) was also developed to verify the validation of the compact LTFET model including the capacitance model. The SPICE simulation results using the Verilog-A LTFET were compared to those obtained using a technology computer-aided-design (TCAD) device simulator. The current-voltage characteristics and capacitance-voltage characteristics of N and P-LTFETs were consistent for all operational bias. The voltage transfer characteristics and transient response of the inverter circuit comprising N and P-LTFETs in series were verified with the TCAD mixed-mode simulation results.
Yu, Yun Seop,Cho, Namki,Oh, Jung Hyun,Hwang, Sung Woo,Ahn, Doyeol American Scientific Publishers 2010 Journal of Nanoscience and Nanotechnology Vol.10 No.5
<P>An analytical and continuous dc model for cylindrical doped surrounding-gate MOSFETs (SGMOSFETs) in the fully-depleted regime is presented. Starting from Poisson's equation, an implicit charge equation is derived approximately by a superposition principle with the exact channel potential and the charge equations in the depletion approximation. Also, a new explicit charge equation is derived from the implicit charge equation. The current equations without any charge-sheet approximation are based on the implicit and explicit charge control models, and both of them are valid for all the operation regions (linear, saturation, and subthreshold) and traces the transition between them without any fitting parameters. In the case of the SGMOSFETs with the fully-depleted condition, both of results simulated from the SGMOSFET models reproduce various 3D simulation results within 5% errors.</P>
Yun Seop Yu,B. H. Choi,안도열,S. H. Hong,S. H. Kim,황성우 한국물리학회 2004 THE JOURNAL OF THE KOREAN PHYSICAL SOCIETY Vol.44 No.1
We introduce a SPICE-compatible model for a oating-dot single-electron memory (FDSEM), which includes both the single-electron box (SEB) model and the modified SOI MOSFET model. In this model, a surface potential model for SOI devices is developed. The accuracy of the developed model is verified with experimental data from FDSEM devices.
Yun Seop Yu 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.4
A full-range analytic drain current model for depletion-mode long-channel surrounding-gate nanowire field-effect transistor (SGNWFET) is proposed. The model is derived from the solution of the 1-D cylindrical Poisson equation which includes dopant and mobile charges, by using the Pao-S모 gradual channel approximation and the full-depletion approximation. The proposed model captures the phenomenon of the bulk conduction mechanism in all regions of device operation (subthreshold, linear, and saturation regions). It has been shown that the continuous model is in complete agreement with the numerical simulations.
Yu, Yun Seop The Institute of Electronics and Information Engin 2013 Journal of semiconductor technology and science Vol.13 No.4
A full-range analytic drain current model for depletion-mode long-channel surrounding-gate nanowire field-effect transistor (SGNWFET) is proposed. The model is derived from the solution of the 1-D cylindrical Poisson equation which includes dopant and mobile charges, by using the Pao-Sah gradual channel approximation and the full-depletion approximation. The proposed model captures the phenomenon of the bulk conduction mechanism in all regions of device operation (subthreshold, linear, and saturation regions). It has been shown that the continuous model is in complete agreement with the numerical simulations.
Device Coupling Effects of Monolithic 3D Inverters
Yu, Yun Seop,Lim, Sung Kyu The Korea Institute of Information and Commucation 2016 Journal of information and communication convergen Vol.14 No.1
The device coupling between the stacked top/bottom field-effect transistors (FETs) in two types of monolithic 3D inverter (M3INV) with/without a metal layer in the bottom tier is investigated, and then the regime of the thickness T<sub>ILD</sub> and dielectric constant ε<sub>r</sub> of the inter-layer distance (ILD), the doping concentration N<sub>d</sub> (N<sub>a</sub>), and length L<sub>g</sub> of the channel, and the side-wall length L<sub>SW</sub> where the stacked FETs are coupled are studied. When N<sub>d</sub> (N<sub>a</sub>) < 10<sup>16</sup> cm<sup>-3</sup> and L<sub>SW</sub> < 20 nm, the threshold voltage shift of the top FET varies almost constantly by the gate voltage of the bottom FET, but when N<sub>d</sub> (N<sub>a</sub>) > 10<sup>16</sup> cm<sup>-3</sup> or L<sub>SW</sub> > 20 nm, the shift decreases and increases, respectively. M3INVs with T<sub>ILD</sub> ≥ 50 nm and ε<sub>r</sub> ≤ 3.9 can neglect the interaction between the stacked FETs, but when T<sub>ILD</sub> or ε<sub>r</sub> do not meet the above conditions, the interaction must be taken into consideration.