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손영찬(Son Yeong Chan),박석홍(Park Seog Hong),유상대(Yu Sang Dae) 한국정보처리학회 1998 정보처리학회논문지 Vol.5 No.12
Due to the high density of integration and the high performance in current integrated circuit, it is more emphasized to verify the electrical connectivity and performance of the circuit extracted from the layout. In this paper, we propose a new algorithm to extract the netlist including the geometric parameters of MOSFETs and the parasitic resistance and capacitance values. Where a set of polygon blocks for routing wires in the layout are described with directional edges and the layout extraction is carried out by checking over the abutment of these blocks on MOSFETs.
마스크 레이아웃 합성을 위한 벡터화한 변을 사용한 블록 분할 기법
손영찬,주이아,유상대,Son, Yeong-Chan,Ju, Ri-A,Yu, Sang-Dae 대한전자공학회 2001 電子工學會論文誌-SD (Semiconductor and devices) Vol.38 No.12
Due to the high density of integration in current integrated circuit layouts, circuit elements must be designed to minimize the effect of parasitic elements and thereby minimize the factors which can degrade circuit performance. Thus, before making a chip, circuit designers should check whether the extracted netlist is correct, and verify from a simulation whether the circuit performance satisfies the design specifications. In this paper, we propose a new block disassembly technique which can extract the geometric parameters of stacked MOSFETs and the distributed RCs of layout blocks. After applying this to the layout of a folded-cascode CMOS operational amplifier, we verified the connectivity and the effect of the components by simulating the extracted netlist with HSPICE. 오늘날 집적회로의 집적도가 증가되고 있기 때문에 회로 소자는 기생성분의 영향을 최소화하고 회로의 성능을 감소시키는 요인을 최소화하도록 설계되어야 한다. 그래서 칩을 제작하기 전에 레이아웃으로부터 추출한 회로가 정확한가를 검증하고 시뮬레이션으로 추출된 회로가 설계사양을 만족하는지를 확인해야 한다. 본 논문에서는 스택 구조의 MOSFET의 기하학적인 파라미터와 레이아웃 배선 블록의 분산 RC를 추출할 수 있는 새로운 블록 분할 기법을 제안한다. 폴디드 캐스코드 CMOS 연산 증폭기의 레이아웃에 이 기법을 작용하여 회로를 추출하고, Hspice로 시뮬레이션을 수행하여 전기적 연결관계와 이들 소자의 영향을 검증하였다.
박석홍,손영찬,유상대 ( Seog Hong Park,Yeong Chan Son,Sang Dae Yu ) 한국센서학회 1996 센서학회지 Vol.5 No.4
This paper presents the optimal design method of SAW filters with arbitrary frequency characteristics. The design program using the unconstrained nonlinear optimization method and FFT algorithm is developed for optimal design of SAW filters with arbitrary frequency characteristics. As a design example, a SAW TV IF filter with asymmetric-amplitude and nonlinear-phase frequency characteristics is designed.
동영상으로부터 외부 조명과 잡음에 견실한 변화 영역 검출
정윤수(Yun Su Chung),김재한(Jae Han Kim),김진석(Jin Seok Kim),손영찬(Yeong Chan Son) 한국정보처리학회 2000 정보처리학회논문지 Vol.7 No.7
This paper propose a method for an external illumination and noise robust change detection in moving image. In proposed method, mean of difference pixels and sum of squared values of difference pixels are calculated from sample block of difference image. And a new test statistic is proposed using these values. The reference method is very sensitive to external illumination and noise, but the proposed test statistic is not sensitive to these. Therefore it is efficient for this method to apply for image having much noise and varying illumination. Experimental results show the improvement of the separated change/non-change region in sequence images having noise and varying illumination.
고속 파이프라인 A/D 변환기를 위한 연산 증폭기의 설계
손영찬,유상대,주리아 경북대학교 전자기술연구소 2001 電子技術硏究誌 Vol.22 No.2
In the design specifications of operational amplifiers which are used in high-speed pipeline A/D converters is analyzed, the technique to design using a design tool of operational amplifiers is proposed. The CMOS operational amplifier usable in 10-b 25-MHz pipelined A/D converters is designed. The operational amplifier designed using 1.2 ㎛ CMOS technology exhibits a do gain of 71 dB, a unity-gain frequency of 195 MHz, a phase margin of 57^*, a slew rate of 186 V/㎲, a output voltage swing of ± 1.1 V, and a power dissipation of 4 mW at 5 V supply voltage and 0.6 pF load. And applying to the S/H amplifier with a gain of 2 and a capacitive load of 0.5 pF the settling time of 14 ns for output voltage swing of 1 ± V satisfied the design specifications.