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Dual-Mode CMOS Power Amplifier Based on Load-Impedance Modulation
Lim, Wonseob,Kang, Hyunuk,Lee, Wooseok,Bae, Jongseok,Oh, Sungjae,Oh, Hansik,Chae, Seunghwan,Hwang, Keum Cheol,Lee, Kang-Yoon,Yang, Youngoo THE INSTITUTE OF ELECTRICAL ENGINEERS 2018 IEEE MICROWAVE AND WIRELESS COMPONENTS LETTERS Vol.28 No.11
<P>This letter presents a dual-mode CMOS power amplifier (PA) that has an improved efficiency using load-impedance modulation in the low-power mode (LPM) and a fully differential operation in the high-power mode (HPM). For the LPM, the transistor in the negative path of the differential pair is turned ON, as a switch, to appropriately modulate the load impedance for the transistor in the positive path using the output balun. An external switch is deployed to turn <TEX>$V_{\text {DD}}$</TEX> OFF for the negative path. In order to verify the proposed concept, a dual-mode CMOS PA IC was designed using a bulk CMOS process and an off-chip output balun, and it was evaluated using the 920-MHz narrow-band Internet of Things signal with a bandwidth of 200 kHz and a peak-to-average power ratio of 5.7 dB. For the HPM, the implemented PA exhibited a gain of 24.1 dB, a power-added efficiency (PAE) of 44.3%, and an adjacent channel leakage power ratio (ACLR) of −33.9 dBc at an average output power of 27.7 dBm. For the LPM, a gain of 19.3 dB, a PAE of 37.7%, and an ACLR of −34.9 dBc were obtained at an average output power of 21.7 dBm.</P>
2.6 GHz GaN-HEMT Power Amplifier MMIC for LTE Small-Cell Applications
Wonseob Lim,Hwiseob Lee,Hyunuk Kang,Wooseok Lee,Kang-Yoon Lee,Keum Cheol Hwang,Youngoo Yang,Cheon-Seok Park 대한전자공학회 2016 Journal of semiconductor technology and science Vol.16 No.3
This paper presents a two-stage power amplifier MMIC using a 0.4 μm GaN-HEMT process. The two-stage structure provides high gain and compact circuit size using an integrated inter-stage matching network. The size and loss of the inter-stage matching network can be reduced by including bond wires as part of the matching network. The two-stage power amplifier MMIC was fabricated with a chip size of 2.0×1.9 mm² and was mounted on a 4×4 QFN carrier for evaluation. Using a downlink LTE signal with a PAPR of 6.5 dB and a channel bandwidth of 10 MHz for the 2.6 GHz band, the power amplifier MMIC exhibited a gain of 30 dB, a drain efficiency of 32%, and an ACLR of -31.4 dBc at an average output power of 36 dBm. Using two power amplifier MMICs for the carrier and peaking amplifiers, a Doherty power amplifier was designed and implemented. At a 6 dB back-off output power level of 39 dBm, a gain of 24.7 dB and a drain efficiency of 43.5% were achieved.
2.6 GHz GaN-HEMT Power Amplifier MMIC for LTE Small-Cell Applications
Lim, Wonseob,Lee, Hwiseob,Kang, Hyunuk,Lee, Wooseok,Lee, Kang-Yoon,Hwang, Keum Cheol,Yang, Youngoo,Park, Cheon-Seok The Institute of Electronics and Information Engin 2016 Journal of semiconductor technology and science Vol.16 No.3
This paper presents a two-stage power amplifier MMIC using a $0.4{\mu}m$ GaN-HEMT process. The two-stage structure provides high gain and compact circuit size using an integrated inter-stage matching network. The size and loss of the inter-stage matching network can be reduced by including bond wires as part of the matching network. The two-stage power amplifier MMIC was fabricated with a chip size of $2.0{\times}1.9mm^2$ and was mounted on a $4{\times}4$ QFN carrier for evaluation. Using a downlink LTE signal with a PAPR of 6.5 dB and a channel bandwidth of 10 MHz for the 2.6 GHz band, the power amplifier MMIC exhibited a gain of 30 dB, a drain efficiency of 32%, and an ACLR of -31.4 dBc at an average output power of 36 dBm. Using two power amplifier MMICs for the carrier and peaking amplifiers, a Doherty power amplifier was designed and implemented. At a 6 dB back-off output power level of 39 dBm, a gain of 24.7 dB and a drain efficiency of 43.5% were achieved.
Hwiseob Lee,Wonseob Lim,Jongseok Bae,Wooseok Lee,Hyunuk Kang,Kang-Yoon Lee,Keum Cheol Hwang,Youngoo Yang IET 2017 IET microwaves, antennas & propagation Vol.11 No.12
<P>This study presents a broadband four-way power combiner/divider for very high frequency (VHF) to ultra-high frequency (UHF) bands using 0 degrees hybrids and impedance transformers based on transmission lines. The 0 degrees hybrids were used as in-phase power combiners or dividers, and 1 : 4 impedance transformers were adopted to transform the impedance so that all input and output ports had a 50 Omega impedance. Each component was analysed using equivalent circuits. The overall size of the implemented four-way power combiner/divider module was 110 x 163 mm(2). Based on the measured S-parameters, an ultrabroad bandwidth from 8.0 to 600 MHz was achieved with an insertion loss < 1.0 dB, reflection coefficients below -10.0 dB, isolation among the ports less than -15.0 dB, and magnitude and phase imbalances less than +/- 0.1 dB and 0.5 degrees, respectively.</P>
Lee, Hwiseob,Lim, Wonseob,Lee, Wooseok,Kang, Hyunuk,Bae, Jongseok,Park, Cheon-Seok,Hwang, Keum Cheol,Lee, Kang-Yoon,Yang, Youngoo IEEE 2017 IEEE microwave and wireless components letters Vol.27 No.3
<P>This letter presents a compact load network for Doherty power amplifier (DPA) integrated circuits (ICs) using p-type left-handed (LH) and right-handed (RH) transmission lines (TLs) based on lumped components. The quarter-wave impedance transformers based on the LH TLs and a compensation method for the internal shunt capacitance using a shunt inductor were adopted for the impedance matching networks. The p-type LH and RH TLs for the matching networks and a combining network can be further simplified by merging adjacent shunt components. In order to verify the proposed load network, a 2.6-GHz DPA IC was designed and fabricated using a 0.4-mu m gallium nitride high-electron-mobility transistor process for small-cell base stations. The overall size of the chip is 1.7 x 1.8 mm(2) and the chip was mounted on a quad flat no-leads package. For a long term evolution signal with a signal bandwidth of 10 MHz and a peak-to-average power ratio of 6.5 dB, a high drain efficiency of 52.2% was obtained at an average output power of 34.0 dBm.</P>
Small-Cell 기지국 시스템을 위한 2.6 GHz GaN-HEMT Doherty 전력증폭기 집적회로 설계
이휘섭(Hwiseob Lee),임원섭(Wonseob Lim),강현욱(Hyunuk Kang),이우석(Wooseok Lee),이형준(Hyoungjun Lee),윤정상(Jeongsang Yoon),이동우(Dongwoo Lee),양영구(Youngoo Yang) 한국전자파학회 2016 한국전자파학회논문지 Vol.27 No.2
본 논문에서는 2.6 GHz에서 동작하는 Doherty 전력증폭기 집적회로를 설계 및 제작하여 평균 전력에서의 효율을 개선하였다. Small-cell 기지국 시스템에 적합하도록 전력 밀도가 높은 GaN-HEMT 공정을 사용하여 설계하였으며, 제작된 Doherty 전력증폭기 집적회로를 QFN 패키지 내부에 수용하여 시스템 적용에 용이하도록 하였다. 제작된 GaN-HEMT Doherty 전력증폭기 집적회로는 10 MHz의 대역폭 및 6.5 dB의 PAPR 특성을 갖는 2.6 GHz LTE 신호에 대하여 평균 전력 33.9 dBm에서 15.8 dB의 전력 이득, 43.0%의 효율 및 —30.0 dBc의 ACLR 특성을 나타낸다. This paper presents a 2.6 GHz Doherty power amplifier IC to enhance the back-off efficiency. In order to apply to small-cell base stations, the Doherty power amplifier was fabricated using GaN-HEMT process for high power density. In addition, the implemented Doherty power amplifier was mounted on a QFN package. The implemented GaN-HEMT Doherty power amplifier was measured using LTE downlink signal with 10 MHz bandwidth and 6.5 dB PAPR for verification. A power gain of 15.8 dB, a drain efficiency of 43.0 %, and an ACLR of —30.0 dBc were obtained at an average output power level of 33.9 dBm.
Optimized Current of the Peaking Amplifier for Two-Stage Doherty Power Amplifier
Lee, Hwiseob,Kwon, Jinhee,Lim, Wonseob,Lee, Wooseok,Kang, Hyunuk,Hwang, Keum Cheol,Lee, Kang-Yoon,Park, Cheon-seok,Yang, Youngoo Professional Technical Group on Microwace Theory a 2017 IEEE Transactions on Microwave Theory and Techniqu Vol. No.
<P>This paper presents a method of improving efficiency for the two-stage Doherty power amplifier (DPA) using the optimized current of the peaking amplifier. The DPA has a two-stage structure for both the carrier and peaking amplifiers. The first stage of the peaking amplifier has an adjusted bias condition for a near Class-B operation, while the first stage of the carrier amplifier has a higher Class-AB operation. The gain expansion of the first stage due to its lower gate bias helps the second stage of the peaking amplifier to be biased for light Class-C operation and to have steeper turn-ON characteristics, which leads higher peak output power and higher back-off efficiency. The two-stage DPA was designed for the 2.655-GHz band. Using a downlink long-term evolution signal with a signal bandwidth of 10 MHz and a peak-to-average power ratio of 6.5 dB, the overall power gain of 25 dB and a peak output power of 54.2 dBm are experimentally obtained. Using an optimized shape of the peaking amplifier's current, a drain efficiency (DE) of 53% and an adjacent channel leakage power ratio of -30 dBc were obtained at an average output power of 47.8 dBm. A DE of 56.8% and an adjacent channel leakage power ratio of -25 dBc were also obtained at an average output power of 49.5 dBm.</P>
전압체배기 구조를 이용한 5.8 ㎓ GaN HEMT F급 정류기
박종진(Jongjin Park),임원섭(Wonseob Lim),양영구(Youngoo Yang) 한국전자파학회 2023 한국전자파학회논문지 Vol.34 No.5
본 논문에서는 전압체배기 구조를 이용한 5.8 ㎓ GaN HEMT F급 정류기에 대한 설계 및 측정결과를 제시한다. 제안된 정류기는 높은 출력 dc 전압 특성을 위해 전압체배기를 사용했고, 고효율 특성 확보를 위해 입력 정합회로에 3차 고조파 임피던스를 개방시키는 기법을 적용했다. 높은 항복전압과 넓은 밴드갭 특성을 갖는 GaN HEMT bare-chip을 다이오드로 사용했고, 이는 높은 입력전력에서 안정적인 동작을 할 수 있다는 장점이 있다. Bare-chip을 PCB와 전기적으로 연결하는 방식을 4가지 제안했고, 최적의 전기적 연결 방식의 검증을 위해 제작 및 측정을 진행했다. 제작된 정류기는 입력 RF 전력 32 ㏈m과 부하저항 1,000 Ω 기준 모든 방식에서 55 % 이상의 RF-dc 변환 효율과 직렬과 병렬 다이오드의 음극을 본드 와이어로, 병렬 다이오드의 양극을 through-wafer via로 PCB와 연결한 회로에서 69 %의 최대 효율을 얻었다. In this study, the design and measurement results of a 5.8 ㎓ GaN HEMT Class-F rectifier using a voltage doubler were proposed. The proposed rectifier employed a voltage doubler for high-output dc voltage characteristics and applied the technique of opening the third-harmonic impedance to an input-matching network to obtain high-efficiency characteristics. A GaN HEMT bare chip with a high breakdown voltage and wide bandgap was used as a diode, which enabled stable operation at a high input power. Four methods of electrically connecting a bare chip to a PCB were proposed, and fabrication and measurements were conducted to verify the optimal electrical connection method. At 5.8 ㎓, with an input RF power of 32 ㏈m and load resistance of 1,000 Ω, the fabricated rectifier exhibited RF-dc conversion efficiency of over 55 % in all methods. Maximum efficiency of 69 % was obtained in a circuit in which the cathodes of series and parallel diodes were connected to the PCB with bond-wires, and the anode of the parallel diode was connected to the PCB with through-wafer via.