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A NOVEL RATE CONTROL ALGORITHM for H.264/AVC
Zhao Min,Takeshi Ikenaga,Satoshi Goto 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
Rate control has become an important part in the whole video coding scheme in order to get obtain consecutive and high quality pictures under a certain bandwidth. This paper presents a novel rate control algorithm for H.264/AVC. Instead of the traditional Mean Absolute Difference (MAD) linear prediction model, which is proposed JVT-G012, a new model is proposed including both temporal and spatial information of MAD. Because calculation complexity of the rate control part is not high comparing with other parts, such as motion estimation, this novel algorithm does not focus on reducing the calculation complexity.
AN EXTENDED SMALL DIAMOND SEARCH ALGORITHM FOR FAST BLOCK MOTION ESTIMATION
Chang-Uk Jeong,Takeshi Ikenaga,Satoshi Goto 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
In this paper, we propose a fast motion estimation algorithm that is suitable for searching both center-biased motion and large motion by applying the small diamond pattern used in some block-matching algorithms (BMA). The search will be terminated by a small diamond search (SDS) method after performing a large search based on a modified three-step search (3SS) strategy. The results of the experiment show an increase about 220% in the search speed compared to that of diamond search (DS) and efficient three-step search (E3SS) in a sequence that represent small motions in objects. Experimental results also demonstrate reasonable search points in the estimation of rough motions in high-resolution images, maintaining a performance better than other fast BMAs in terms of PSNR.
A resource preserved MAC protocol for QoS provided UWB ad hoc networks
Jiachen Zhou,Yiqing Huang,Takeshi Ikenaga 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
This paper proposes a resource preserved medium access control (MAC) protocol which provides Quality of Service (QoS) support for multimedia applications in ultra-wideband (UWB) ad hoc network. The proposed protocol accounts for the UWB unique characteristics while considering the QoS requirements. The evaluation results in throughputs, end to end delay, power consumption and power utilization show that, the proposed algorithms achieve a balance work between the throughputs and power consumption.
A Novel Fast Block Type Decision Algorithm for Intra Prediction in H.264/AVC High Profile
Tianruo Zhang,Guifen Tian,Takeshi Ikenaga,Satoshi Goto 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
The latest video coding standard H.264/AVC significantly increases video compression efficiency but also increases computation complexity. Intra prediction is an important part in H.264/AVC encoder and it’s also time consuming. This paper proposes a fast block type decision algorithm which can reduce intra prediction’s computation complexity with slight PSNR reduction. The relation between intra prediction block type and macrblocks’ frequency feature has been discussed. Based on these observations, this algorithm can select only one or two block type in 4×4, 8×8 and 16×16 intra prediction instead of three of them. Experimental results show that this algorithm is suitable to perform on large frame size sequences.
A High Throughput Multiple Transform Architecture for H.264/AVC Fidelity Range Extensions
Yao Ma,Yang Song,Takeshi Ikenaga,Satoshi Goto 대한전자공학회 2007 Journal of semiconductor technology and science Vol.7 No.4
In this paper, a high throughput multiple transform architecture for H.264 Fidelity Range Extensions (FRExt) is proposed. New techniques are adopted which (1) regularize the 8×8 integer forward and inverse DCT transform matrices, (2) divide them into four 4 × 4 sub-matrices so that simple fast butterfly algorithm can be used, (3) because of the similarity of the sub-matrices, mixed butterflies are proposed that all the sub-matrices of 8 × 8 and matrices of 4×4 forward DCT (FDCT), inverse DCT (IDCT) and Hadamard transform can be merged together. Based on these techniques, a hardware architecture is realized which can achieve throughput of 1.488Gpixel/s when processing either 4×4 or 8×8 transform. With such high throughput, the design can satisfy the critical requirement of the real-time multi-transform processing of High Definition (HD) applications such as High Definition DVD (HD-DVD) (1920x1080@60Hz) in H.264/AVC FRExt. This work has been synthesized using Rohm 0.18um library. The design can work on a frequency of 93MHz and throughput of 1.488Gpixel/s with a cost of 56440 gates.
A High Throughput Multiple Transform Architecture for H.264/AVC Fidelity Range Extensions
Ma, Yao,Song, Yang,Ikenaga, Takeshi,Goto, Satoshi The Institute of Electronics and Information Engin 2007 Journal of semiconductor technology and science Vol.7 No.4
In this paper, a high throughput multiple transform architecture for H.264 Fidelity Range Extensions (FRExt) is proposed. New techniques are adopted which (1) regularize the $8{\times}8$ integer forward and inverse DCT transform matrices, (2) divide them into four $4{\times}4$ sub-matrices so that simple fast butterfly algorithm can be used, (3) because of the similarity of the sub-matrices, mixed butterflies are proposed that all the sub-matrices of $8{\times}8$ and matrices of $4{\times}4$ forward DCT (FDCT), inverse DCT (IDCT) and Hadamard transform can be merged together. Based on these techniques, a hardware architecture is realized which can achieve throughput of 1.488Gpixel/s when processing either $4{\times}4\;or\;8{\times}8$ transform. With such high throughput, the design can satisfy the critical requirement of the real-time multi-transform processing of High Definition (HD) applications such as High Definition DVD (HD-DVD) ($1920{\times}1080@60Hz$) in H.264/AVC FRExt. This work has been synthesized using Rohm 0.18um library. The design can work on a frequency of 93MHz and throughput of 1.488Gpixel/s with a cost of 56440 gates.
Zhewen ZHENG,Yiqing HUANG,Qin LIU,Takeshi IKENAGA 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
H.264/AVC performs rate-distortion optimization (RDO) in order to select the best coding modes with best coding efficiency. However, computation complexity is also increased. In this paper, a fast intra mode decision algorithm is proposed. With both the magnitude and the orientation of the local edge information, most proper block mode is selected from 4×4, 8×8 and 16×16 block modes. Then by the edge information obtained from previous step, candidate prediction modes are decided for the chosen block modes. The number of modes investigated in RDO can be reduced to 36 or 48 in common case instead of 736 in full search. Simulation results show that the proposed algorithm saves about 75% coding time with negligible PSNR loss and bit-rate increase compared with full search.
Bit-Usage Analysis Based Frame Layer QP Adjustment for H.264/AVC Rate Control at Low Bit-Rate
Shuijiong WU,Yiqing HUANG,Qin LIU,Takeshi IKENAGA 대한전자공학회 2009 ITC-CSCC :International Technical Conference on Ci Vol.2009 No.7
To regulate the output video streaming, rate control is introduced into practical video codec. It allocates the bit budget, dynamically adjusts quantization parameter (QP) to achieve target bit-rate while keeping the coding quality. This paper presents a bit analysis based frame layer QP adjustment for H.264/AVC rate control at low bit-rate. The bit generation of previous coded frames, bit estimation of current frame and the remaining bit resources are utilized to get estimation for current coding status. Backward and forward bit usage measurements are combined to make a global judgment based on the whole sequence. Then the QP computed for current frame is further adjusted by the bit usage judgment. Simulation results verify the performance of proposed algorithm. Compared with the recommended rate control in H.264/AVC reference software JM13.2, a gain up to 0.3 ㏈ on peak-signal-noise-ratio (PSNR) is observed. And the rate mismatch is reduced about 84 % for tested sequences.
Development of Industrial Robot System with 5th Generation Mobile Communication System
Atsuki Yokota,Sora Honda,Kei Yamafuku,Takeshi Nishida,Takeshi Ikenaga,Naoki Mori,Akira Matsunaga,Kakeru Maruyama,Kyohiro Yoshida,Shintaro Osada 제어로봇시스템학회 2019 제어로봇시스템학회 국제학술대회 논문집 Vol.2019 No.10
We experimented the configuration of a 5th generation mobile communication system (5G) for factory automation (FA) systems consisting of industrial robots and three-dimensional measurement sensors. We examined the configuration of system components, on the basis of which we developed an experimental FA system. In addition, we confirmed that the need for communication lines is eliminated as 5G greatly reduces the production preparation time when rearranging the parts of the developed FA system.
A power-saving 1Gbps Irregular LDPC Decoder based on high-efficiency messagepassing
Wenming Tang,Wen Ji,Xianghui Wei,Takeshi Ikenaga,Satoshi Goto 대한전자공학회 2008 ITC-CSCC :International Technical Conference on Ci Vol.2008 No.7
In this paper we proposed a partially-parallel decoder for irregular LDPC codes from IEEE802.11n standards. Our proposed decoder adopts high-efficiency message-passing algorithm and uses the min-sum algorithm handle the message-passing to reduce the hardware implementation complexity and area, and keep high throughput. Considering reducing the power consumption, we used half-registers and half-memory to store the temporary intrinsic messages. The wasted motion of shiftregister was suppressed. This strategy would save us higher as 30% power under good channel condition. The synthesis result in TSMC 0.18um COMS technology demonstrated that for (1296,324) irregular LDPC code achieved high throughput (1.05Gbps) at the frequency of 200㎒, with 6% area reduction.