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Park, Sungkyung,Park, Chester Sungchung World Scientific Publishing Company 2017 Journal of circuits, systems, and computers Vol.26 No.9
<P>Deeply embedded applications demand small area, low power, high code density, and low design complexity for high adaptability. Both a 16-bit microprocessor with a 4G byte linear memory space and a 4-bit processor are proposed and designed to achieve these goals. Hardware reuse and sharing, multicycle architecture, compact instruction set architecture, and counter-based instruction decoder are utilized to reduce gate count. As a result, gate count and power dissipation of the synthesized ASIC gate-level netlists of 16-bit and 4-bit processors are less than 14,000, 1,490, 0.5<TEX>$ \,$</TEX>m W, and 0.06<TEX>$ \,$</TEX>m W, respectively, at 10<TEX>$ \,$</TEX>MHz in a 0.18<TEX>$ \,$</TEX><TEX>$ \mu $</TEX>m digital CMOS technology. The proposed 16-bit and 32-bit processors are extendable instruction set computers whose high code density is demonstrated to reduce code bytes by 40% over a reduced instruction set computer. The pipelined EISC processor only consumes 50<TEX>$ \,$</TEX><TEX>$ \mu $</TEX>W/MHz with 10,800 gates in a 0.18<TEX>$ \,$</TEX><TEX>$ \mu $</TEX>m CMOS process.</P>
Fractional-N phase-locked loop for split and direct automatic frequency control in A-GPS
Park, Chester Sungchung,Park, Sungkyung Informa UK (TaylorFrancis) 2018 International journal of electronics Vol.105 No.7
<P>A low-power mixed-signal phase-locked loop (PLL) is modelled and designed for the DigRF interface between the RF chip and the modem chip. An assisted-GPS or A-GPS multi-standard system includes the DigRF interface and uses the split automatic frequency control (AFC) technique. The PLL circuitry uses the direct AFC technique and is based on the fractional-N architecture using a digital delta-sigma modulator along with a digital counter, fulfilling simple ultra-high-resolution AFC with robust digital circuitry and its timing. Relative to the output frequency, the measured AFC resolution or accuracy is <5 parts per billion (ppb) or on the order of a Hertz. The cycle-to-cycle rms jitter is <6ps and the typical settling time is <30s. A spur reduction technique is adopted and implemented as well, demonstrating spur reduction without employing dithering. The proposed PLL includes a low-leakage phase-frequency detector, a low-drop-out regulator, power-on-reset circuitry and precharge circuitry. The PLL is implemented in a 90-nm CMOS process technology with 1.2V single supply. The overall PLL draws about 1.1mA from the supply.</P>
Park, Chester Sungchung,Park, Sungkyung 한국정보통신학회 2015 Journal of information and communication convergen Vol.13 No.4
A decimation chain for multi-standard reconfigurable radios is presented for 900-MHz and 1,900-MHz dual-band cellular standards with a data interpolator based on the Lagrange method for adjusting the variable data rate to a fixed data rate appropriate for each standard. The two proposed configurations are analyzed and compared to provide insight into aliasing and the signal bandwidth by means of a newly introduced measure called interpolation error. The average interpolation error is reduced as the ratio of the sampling frequency to the signal BW is increased. The decimation chain and the multi-rate analog-to-digital converter are simulated to compute the interpolation error and the output signal-to-noise ratio. Further, a method to operate the above-mentioned chain under a compressed mode of operation is proposed in order to guarantee continuous packet connectivity for inter-radio-access technologies. The presented decimation chain can be applied to LTE, WCDMA, GSM multi-mode multi-band digital front-end which will ultimately lead to the software-defined radio.
낮은 복잡도의 Deeply Embedded 중앙처리장치 및 시스템온칩 구현
박성정(Park, Chester Sungchung),박성경(Park, Sungkyung) 한국산학기술학회 2016 한국산학기술학회논문지 Vol.17 No.3
중앙처리장치를 중심으로 하는 각종 내장형 시스템은 현재 각종 산업에 매우 광범위하게 쓰이고 있다. 특히 사물인터넷 등의 deeply embedded (심층 내장형) 시스템은 저비용, 소면적, 저전력, 빠른 시장 출시, 높은 코드 밀도 등을 요구한다.본 논문에서는 이러한 요구 조건을 만족시키는 중앙처리장치를 제안하고, 이를 중심으로 한 시스템온칩 플랫폼을 소개한다.제안하는 중앙처리장치는 16 비트라는 짧은 명령어로만 이루어진 확장형 명령어 집합 구조를 갖고 있어 코드 밀도를 높일 수 있다. 그리고, 다중사이클 아키텍처, 카운터 기반 제어 장치, 가산기 공유 등을 통하여 로직 게이트가 차지하는 면적을 줄였다. 이 코어를 중심으로, 코프로세서, 명령어 캐시, 버스, 내부 메모리, 외장 메모리, 온칩디버거 및 주변 입출력 장치들로 이루어진 시스템온칩 플랫폼을 개발하였다. 개발된 시스템온칩 플랫폼은 변형된 하버드 구조를 갖고 있어, 메모리 접근 시 필요한 클락 사이클 수를 감소시킬 수 있었다. 코어를 포함한 시스템온칩 플랫폼은 상위 언어 수준과 어셈블리어 수준에서 모의실험 및 검증하였고, FPGA 프로토타이핑과 통합형 로직 분석 및 보드 수준 검증을 완료하였다. 0.18μm 디지털 CMOS공정과 1.8V 공급 전압 하에서 ASIC 프론트-엔드 게이트 수준 로직 합성 결과, 50MHz 동작 주파수에서 중앙처리장치 코어의 논리 게이트 개수는 7700 수준이었다. 개발된 시스템온칩 플랫폼은 초소형 보드의 FPGA에 내장되어 사물인터넷 분야에 응용된다. This paper proposes a low-complexity central processing unit (CPU) that is suitable for deeply embedded systems, including Internet of things (IoT) applications. The core features a 16-bit instruction set architecture (ISA) that leads to high code density, as well as a multicycle architecture with a counter-based control unit and adder sharing that lead to a small hardware area. A co-processor, instruction cache, AMBA bus, internal SRAM, external memory, on-chip debugger (OCD), and peripheral I/Os are placed around the core to make a system-on-a-chip (SoC) platform. This platform is based on a modified Harvard architecture to facilitate memory access by reducing the number of access clock cycles. The SoC platform and CPU were simulated and verified at the C and the assembly levels, and FPGA prototyping with integrated logic analysis was carried out. The CPU was synthesized at the ASIC front-end gate netlist level using a 0.18μm digital CMOS technology with 1.8V supply, resulting in a gate count of merely 7700 at a 50MHz clock speed. The SoC platform was embedded in an FPGA on a miniature board and applied to deeply embedded IoT applications.
Simple Design of Detector in the Presence of Frequency Offset for IEEE 802.15.4 LR-WPANs
Daesik Park,Sungchung Park, C.,Kwyro Lee IEEE 2009 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS PART 2 E Vol.56 No.4
<P>A simple detector for orthogonal modulation that is robust to large frequency offsets is proposed. The complexity of the detector is significantly reduced by implementing the correlator using multiplexers instead of complex floating-point multiplications. The performance of this design is comparable to the optimal value obtained by double correlation in offset quadrature phase-shift keying (O-QPSK) and nearly reaches that of noncoherent maximum likelihood (NCOHML) detection with 10-ppm frequency offset in the additive white Gaussian noise (AWGN) channel. Therefore, the proposed design can be used in low-cost and low-power IEEE 802.15.4 low-rate wireless personal area network (LR-WPAN) applications.</P>