http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
Lee, Minwoong,Cho, Seongik,Lee, Namho,Kim, Jongyeol Elsevier 2018 MICROELECTRONIC ENGINEERING Vol.200 No.-
<P><B>Abstract</B></P> <P>The n-type metal-oxide-semiconductor field-effect transistor (n-MOSFET) produced in the widely used CMOS bulk process takes radiation damage by the total ionizing dose (TID) effects in radiation environments, so the radiation-tolerant properties of semiconductor integrated-circuits (ICs) used in high-radiation environments is a critical issue. The formation method of the isolation oxide module (IOM), which induces the radiation-induced leakage currents, differs depending on the chip density of the CMOS bulk process. In this paper, we designed and fabricated I-gate n-MOSFETs for bulk process and analyzed the radiation-tolerant characteristics according to IOM. The I-gate n-MOSFET chips are fabricated using the shallow trench isolation (STI) 0.18um and local oxidation of silicon (LOCOS) 0.35um processes of the CMOS bulk process. Tests and evaluation of the TID effects on the chips are carried out by irradiating a total cumulative dose up to 2 Mrad(Si). As the results, in the standard n-MOSFET, the leakage currents of the LOCOS and STI processes are 27.7uA and 16.4uA, and in I-gate n-MOSEFT, are 1.1uA and 0.7uA. The leakage currents of standard n-MOSFET increased by about 25 times before and after irradiation, but the electric characteristics of I-gate n-MOSFET is maintained regardless of the process. Therefore, the process versatility of the I-gate n-MOSFET with the radiation-tolerant performance has been verified.</P> <P><B>Highlights</B></P> <P> <UL> <LI> Radiation-induced TID effects that forms the leakage current of the electronic device. </LI> <LI> Implementation of n-MOSFET with I-gate structure to block leakage current. </LI> <LI> Verification of radiation-tolerance characteristics in LOCOS and STI process through TID effect test. </LI> <LI> Process versatility for designing radiation integrated circuits. </LI> </UL> </P> <P><B>Graphical abstract</B></P> <P>[DISPLAY OMISSION]</P>
Memristor Emulator for Memristor Circuit Applications
Hyongsuk Kim,Sah, M. Pd,Changju Yang,Seongik Cho,Chua, L. O. IEEE 2012 IEEE Transactions on Circuits and Systems I: Regul Vol.59 No.10
<P>A memristor emulator which imitates the behavior of a TiO<SUB>2</SUB> memristor is presented. Our emulator is built from off-the-shelf solid state components. To develop real world memristor circuit applications, the emulator can be used for breadboard experiments in real time. Two or more memristor emulators can be connected in serial, in parallel, or in hybrid (serial and parallel combined) with identical or opposite polarities. With a simple change of connection, each memristor emulator can be switched between a decremental configuration or an incremental configuration. The hardware and spice simulation of the proposed emulator showed promising results that provides an alternative solution of hp TiO<SUB>2</SUB> memristor model in real circuit.</P>
Small-area and compact CMOS emulator circuit for CMOS/nanoscale memristor co-design
Shin, SangHak,Choi, Jun-Myung,Cho, Seongik,Min, Kyeong-Sik Springer 2013 NANOSCALE RESEARCH LETTERS Vol.8 No.1
<P>In this paper, a CMOS emulator circuit that can reproduce nanoscale memristive behavior is proposed. The proposed emulator circuit can mimic the pinched hysteresis loops of nanoscale memristor memory's current-voltage relationship without using any resistor array, complicated circuit blocks, etc. that may occupy very large layout area. Instead of using a resistor array, other complicated circuit blocks, etc., the proposed emulator circuit can describe the nanoscale memristor's current-voltage relationship using a simple voltage-controlled resistor, where its resistance can be programmed by the stored voltage at the state variable capacitor. Comparing the layout area between the previous emulator circuit and the proposed one, the layout area of the proposed emulator circuit is estimated to be 32 times smaller than the previous emulator circuit. The proposed CMOS emulator circuit of nanoscale memristor memory will be very useful in developing hybrid circuits of CMOS/nanoscale memristor memory.</P>
총이온화선량 효과에 내성을 갖는 CMOS NOR 게이트 설계 및 검증
이민웅(Minwoong Lee),이남호(Namho Lee),김종열(Jongyeol Kim),황영관(Younggwan Hwang),김영웅(Youngwoong Kim),송근영(Keunyoung Song),조성익(Seongik Cho) 대한전기학회 2021 대한전기학회 학술대회 논문집 Vol.2021 No.10
총이온화선량(Total ionizing dose, TID) 효과는 원전이나 우주 환경에서 누적방사선에 의한 전자부품의 성능저하 및 오동작의 피해를 발생시킨다. 특히, CMOS 기반의 집적회로에서 n형 MOSFET은 이러한 TID 효과에 취약한 특성을 갖는다. 누적방사선 증가에 따라 n형 MOSFET는 누설전류가 증가하고 전자 회로 및 장치 전체에 비이상적인 특성을 유발한다. 결국, 방사선 환경 노출된 전자장치가 정상적인 기능을 수행하기 위해서는 TID 효과에 대한 내성을 확보해야한다. 본 논문에서는 0.18㎛ CMOS 벌크공정에서 누적방사선에 취약한 n-MOSFET의 내성강화 구조를 적용하여 로직회로 중 NOR 게이트를 설계·제작하였으며 방사선 실측평가를 통하여 누적방사선량 20 kGy(Si)까지 내성을 검증하였다.