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A Subthreshold Swing Model for Symmetric Double-Gate (DG) MOSFETs with Vertical Gaussian Doping
Tiwari, Pramod Kumar,Jit, S. The Institute of Electronics and Information Engin 2010 Journal of semiconductor technology and science Vol.10 No.2
An analytical subthreshold swing model is presented for symmetric double-gate (DG) MOSFETs with Gaussian doping profile in vertical direction. The model is based on the effective conduction path effect (ECPE) concept of uniformly doped symmetric DG MOSFETs. The effect of channel doping on the subthreshold swing characteristics for non-uniformly doped device has been investigated. The model also includes the effect of various device parameters on the subthreshold swing characteristics of DG MOSFETs. The proposed model has been validated by comparing the analytical results with numerical simulation data obtained by using the commercially available $ATLAS^{TM}$ device simulator. The model is believed to provide a better physical insight and understanding of DG MOSFET devices operating in the subthreshold regime.
A Subthreshold Swing Model for Symmetric Double-Gate (DG) MOSFETs with Vertical Gaussian Doping
Pramod Kumar Tiwari,S. Jit 대한전자공학회 2010 Journal of semiconductor technology and science Vol.10 No.2
An analytical subthreshold swing model is presented for symmetric double-gate (DG) MOSFETs with Gaussian doping profile in vertical direction. The model is based on the effective conduction path effect (ECPE) concept of uniformly doped symmetric DG MOSFETs. The effect of channel doping on the subthreshold swing characteristics for non-uniformly doped device has been investigated. The model also includes the effect of various device parameters on the subthreshold swing characteristics of DG MOSFETs. The proposed model has been validated by comparing the analytical results with numerical simulation data obtained by using the commercially available ATLAS™ device simulator. The model is believed to provide a better physical insight and understanding of DG MOSFET devices operating in the subthreshold regime.
Theoretical and Experimental Study of UV Detection Characteristics of Pd/ZnO Nanorod Schottky Diodes
Shaivalini Singh,Pramod Kumar Tiwari,Hemant Kumar,Yogesh Kumar,Gopal Rawat,Sanjay Kumar,Kunal Singh,Ekta Goel,S. Jit,박시현 성균관대학교(자연과학캠퍼스) 성균나노과학기술원 2017 NANO Vol.12 No.11
In this work, we report theoretical and experimental study of Pd/ZnO nanorod (NR) Schottky diodes-based ultraviolet photodetector (UV-PD). The ZnO-NRs are deposited on indium tin oxide (ITO) coated glass substrates by using a low-temperature hydrothermal method. The surface morphology of the ZnO-NRs film is characterized by X-ray diffraction (XRD) and scanning electron microscopy (SEM). The SEM image shows vertically grown NRs with uniformity, and XRD shows the preferred (002) orientation of ZnO-NR films. The current–voltage characteristics of Pd/ZnO-NR Schottky diodes are studied under dark and UV light. A voltage bias from -1V to +1V is applied and the ratio of photocurrent to dark current was ( ~0.17 x 10 2 at V = 0.5V) calculated from the I–V curve. The value of responsivity was found to be 0.111A/W at λ = 365 nm and at bias = 0.50 V. An approximated UV-PD structure has also been numerically simulated using three-dimensional (3D) device simulator from Visual TCAD of Cogenda International. The simulated I–V characteristics have also been plotted under both dark and light conditions. The simulated results are found to be following the nature of experimental results.
Binay Binod Kumar,Shubham Kumar,Pramod Kumar Tiwari,Aniruddh Bahadur Yadav,Sarvesh Dubey,Kunal Singh 한국전기전자재료학회 2024 Transactions on Electrical and Electronic Material Vol.25 No.3
This paper explores possibility of device as well as circuit performance enhancement in the bottom gate ZnO based TFT via Mg and Cd material doping. DC, Analog & RF performance, Energy effi ciency and Noise analysis were erformed for both doped (i.e., MgyZn1−yO and CdxZn1−xO ) and undoped ZnO channel TFT structures. Further, successful ircuit implementation of these devices was done in resistive inverter and AMLCD pixel display circuits. Performance wise both MgyZn1−yO and CdxZn1−xO channel TFTs were found to be superior against its undoped variant. ~ 376%, ~ 105% nd ~ 162% are the percentage improvement in (ION∕IOFF) ratio, fi eld eff ect mobility (μFE) and eff ective mobility μeff) for CdxZn1−xO based TFT with respect to ZnO based TFT, same parameters show ~ 194%, ~ 103% and ~ 133% ercentage improvement for the case of MgyZn1−yO TFT. Also, ~ 23% is percentage decrease in subthreshold swing (SS) for CdxZn1−xO based TFT with respect to ZnO based, whereas ~ 11% is percentage decrement for MgyZn1−yO . Intrinsic gate delay, the percentage decrement is ~ 54.15 and ~ 59.95% for MgyZn1−yO and CdxZn1−xO respectively w.r.t ZnO. Both the CdxZn1−xO and MgyZn1−yO TFT shows unanimous decrease in delay for the resistive inverter as well as AMLCD pixel display circuits. The reported results shows that bottom gate CdxZn1−xO TFT has better performance for bove-mentioned performance parameters. The numerical simulations are performed on Silvaco ATLAS TCAD simulator.
Mirgender Kumar,Sarvesh Dubey,Pramod Kumar Tiwari,S. Jit 한국물리학회 2013 Current Applied Physics Vol.13 No.8
The SiliconeGermanium-on-Insulator (SGOI) and Silicon-on-Insulator (SOI) based MOS structures are spearheading the strained-Si technology. The present work compares the subthreshold characteristics of two short-channel back-gated (BG) strained-Si-on-SGOI (SSGOI) and BG strained-Si-on-Insulator (SSOI)MOSFETs, and provides some solutions to overcome the degradation in subthreshold characteristics with the unrelenting downscaling of the devices. Subthreshold behaviors of the MOS structures are based on surface potential model which is determined by solving the 2D Poisson’s equation with suitable boundary conditions by evanescent mode analysis for both of the MOS structures. The closed form expressions for threshold voltage, subthreshold current and subthreshold swing have been derived for symmetrical as well as independent gate operation (IGO). In addition, the Electrostatic integrity (EI)factors for SSOI and SSGOI MOS structures have been estimated and compared with Double-Gate (DG)MOSFET. The numerical simulation results, obtained by ATLAS, a 2D device simulator from Silvaco, have been used to assess the validity of the models.
Bhushan, Shiv,Sarangi, Santunu,Gopi, Krishna Saramekala,Santra, Abirmoya,Dubey, Sarvesh,Tiwari, Pramod Kumar The Institute of Electronics and Information Engin 2013 Journal of semiconductor technology and science Vol.13 No.4
In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium ($Si_{1-X}Ge_X$) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from two-dimensional (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson's equation with suitable boundary conditions in both the strained-Si layer and relaxed $Si_{1-X}Ge_X$ layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS$^{TM}$, a 2D device simulator from Silvaco Inc.
Shiv Bhushan,Santunu Sarangi,Gopi Krishna S.,Abirmoya Santra,Sarvesh Dubey,Pramod Kumar Tiwari 대한전자공학회 2013 Journal of semiconductor technology and science Vol.13 No.4
In this paper, an analytical threshold voltage model is developed for a short-channel double-material-gate (DMG) strained-silicon (s-Si) on silicon-germanium (Si1-x Gex) MOSFET structure. The proposed threshold voltage model is based on the so called virtual-cathode potential formulation. The virtual-cathode potential is taken as minimum channel potential along the transverse direction of the channel and is derived from tow-dimensional (2D) potential distribution of channel region. The (2D) potential distribution of channel region. The 2D channel potential is formulated by solving the 2D Poisson"s equation with suitable boundary conditions in both the strained-Si layer and relaxed Si1-x Gex layer. The effects of a number of device parameters like the Ge mole fraction, Si film thickness and gate-length ratio have been considered on threshold voltage. Further, the drain induced barrier lowering (DIBL) has also been analyzed for gate-length ratio and amount of strain variations. The validity of the present 2D analytical model is verified with ATLAS<SUP>TM</SUP>, a 2D device simulator from Silvaco Inc.