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조성재,Shinichi O’uchi,Kazuhiko Endo,김상완,Younghwan Son,Meishoku Masahara,James S. Harris, Jr.,박병국,강인만 대한전자공학회 2010 Journal of semiconductor technology and science Vol.10 No.4
In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT)model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.
Cho, Seong-Jae,O'uchi, Shinichi,Endo, Kazuhiko,Kim, Sang-Wan,Son, Young-Hwan,Kang, In-Man,Masahara, Meishoku,Harris, James S.Jr,Park, Byung-Gook The Institute of Electronics and Information Engin 2010 Journal of semiconductor technology and science Vol.10 No.4
In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-nm node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-nm channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 nm to suppress GIDL effectively for reliable low standby power (LSTP) operation.
Seongjae Cho,Shinichi O’uchi,Kazuhiko Endo,Sang Wan Kim,Younghwan Son,In Man Kang,Meishoku Masahara,James S. Harris,Byung-Gook Park 대한전자공학회 2010 Journal of semiconductor technology and science Vol.10 No.4
In this work, reliable methodology for device design is presented. Based on this method, the underlap length has been optimized for minimizing the gateinduced drain leakage (GIDL) in a 22-㎚ node 4-terminal (4-T) silicon-on-insulator (SOI) fin-shaped field effect transistor (FinFET) by TCAD simulation. In order to examine the effects of underlap length on GIDL more realistically, doping profile of the source and drain (S/D) junctions, carrier lifetimes, and the parameters for a band-to-band tunneling (BTBT) model have been experimentally extracted from the devices of 90-㎚ channel length as well as pnjunction test element groups (TEGs). It was confirmed that the underlap length should be near 15 ㎚ to suppress GIDL effectively for reliable low standby power (LSTP) operation.