http://chineseinput.net/에서 pinyin(병음)방식으로 중국어를 변환할 수 있습니다.
변환된 중국어를 복사하여 사용하시면 됩니다.
A Scaling Trend of Variation-Tolerant SRAM Circuit Design in Deeper Nanometer Era
Hiroyuki Yamauchi 대한전자공학회 2009 Journal of semiconductor technology and science Vol.9 No.1
Evaluation results about area scaling capabilities of various SRAM margin-assist techniques for random VT variability issues are described. Various efforts to address these issues by not only the cell topology changes from 6T to 8T and 10T but also incorporating multiple voltage-supply for the cell terminal biasing and timing sequence controls of read and write are comprehensively compared in light of an impact on the required area overhead for each design solution given by ever increasing VT variation (σVT). Two different scenarios which hinge upon the EOT (Effective Oxide Thickness) scaling trend of being pessimistic and optimistic, are assumed to compare the area scaling trends among various SRAM solutions for 32 ㎚ process node and beyond. As a result, it has been shown that 6T SRAM will be allowed long reign even in 15 ㎚ node if σVT can be suppressed to < 70 ㎷ thanks to EOT scaling for LSTP (Low Standby Power) process.
A Low Vth SRAM Reducing Mismatch of Cell-Stability with an Elevated Cell Biasing Scheme
Hiroyuki Yamauchi 대한전자공학회 2010 Journal of semiconductor technology and science Vol.10 No.2
A lower-threshold-voltage (LVth) SRAM cell with an elevated cell biasing scheme, which enables to reduce the random threshold-voltage (Vth) variation and to alleviate the stability-degradation caused by word-line (WL) and cell power line (VDDM) disturbed accesses in row and column directions, has been proposed. The random Vth variation (σVth) is suppressed by the proposed LVth cell. As a result, the LVth cell reduces the variation of static noise margin (SNM) for the data retention, which enables to maintain a higher SNM over a larger memory size, compared with a conventionally being used higher Vth (HVth) cell. An elevated cell biasing scheme cancels the substantial trade-off relationship between SNM and the write margin (WRTM) in an SRAM cell. Obtained simulation results with a 45-㎚ CMOS technology model demonstrate that the proposed techniques allow sufficient stability margins to be maintained up to 6σ level with a 0.5-V data retention voltage and a 0.7-V logic bias voltage.
A Scaling Trend of Variation-Tolerant SRAM Circuit Design in Deeper Nanometer Era
Yamauchi, Hiroyuki The Institute of Electronics and Information Engin 2009 Journal of semiconductor technology and science Vol.9 No.1
Evaluation results about area scaling capabilities of various SRAM margin-assist techniques for random $V_T$ variability issues are described. Various efforts to address these issues by not only the cell topology changes from 6T to 8T and 10T but also incorporating multiple voltage-supply for the cell terminal biasing and timing sequence controls of read and write are comprehensively compared in light of an impact on the required area overhead for each design solution given by ever increasing $V_T$ variation (${\sigma}_{VT}$). Two different scenarios which hinge upon the EOT (Effective Oxide Thickness) scaling trend of being pessimistic and optimistic, are assumed to compare the area scaling trends among various SRAM solutions for 32 nm process node and beyond. As a result, it has been shown that 6T SRAM will be allowed long reign even in 15 nm node if ${\sigma}_{VT}$ can be suppressed to < 70 mV thanks to EOT scaling for LSTP (Low Standby Power) process.
A Low Vth SRAM Reducing Mismatch of Cell-Stability with an Elevated Cell Biasing Scheme
Yamauchi, Hiroyuki The Institute of Electronics and Information Engin 2010 Journal of semiconductor technology and science Vol.10 No.2
A lower-threshold-voltage (LVth) SRAM cell with an elevated cell biasing scheme, which enables to reduce the random threshold-voltage (Vth) variation and to alleviate the stability-degradation caused by word-line (WL) and cell power line (VDDM) disturbed accesses in row and column directions, has been proposed. The random Vth variation (${\sigma}Vth$) is suppressed by the proposed LVth cell. As a result, the LVth cell reduces the variation of static noise margin (SNM) for the data retention, which enables to maintain a higher SNM over a larger memory size, compared with a conventionally being used higher Vth (HVth) cell. An elevated cell biasing scheme cancels the substantial trade-off relationship between SNM and the write margin (WRTM) in an SRAM cell. Obtained simulation results with a 45-nm CMOS technology model demonstrate that the proposed techniques allow sufficient stability margins to be maintained up to $6{\sigma}$ level with a 0.5-V data retention voltage and a 0.7-V logic bias voltage.
A Scaling Trend of Variation-Tolerant SRAM Circuit Design in Deeper Nanometer Era
Hiroyuki Yamauchi 대한전자공학회 2009 Journal of semiconductor technology and science Vol.8 No.1
Evaluation results about area scaling capabilities of various SRAM margin-assist techniques for random VT variability issues are described. Various efforts to address these issues by not only the cell topology changes from 6T to 8T and 10T but also incorporating multiple voltage-supply for the cell terminal biasing and timing sequence controls of read and write are comprehensively compared in light of an impact on the required area overhead for each design solution given by ever increasing VT variation (σVT). Two different scenarios which hinge upon the EOT (Effective Oxide Thickness) scaling trend of being pessimistic and optimistic, are assumed to compare the area scaling trends among various SRAM solutions for 32 nm process node and beyond. As a result, it has been shown that 6T SRAM will be allowed long reign even in 15 nm node if σVT can be suppressed to < 70 mV thanks to EOT scaling for LSTP (Low Standby Power) process.
山內博之(Yamauchi Hiroyuki),淸水孝司(Shimizu Takashi) 한국일본문화학회 2001 日本文化學報 Vol.10 No.-
The purpose of this paper is clarifying the difference between "-ga mieru" and "-ga mirareru". "Mirareru" is the potential form of the verb "miru" and "mieru" is the "jihatsu" form of it, which is a kind of potential form but not the regular potential form. Therefor "mieru" and "mirareru" belong to the quite different grammatical categories. The both, however, have much similarity in meaning. There are actually many situations where both "mieru" and "mirareru" seem to be usable. In such situations "mieru" is preferred to "mirareru" because Japanese language has the tendency that the expressions of "jihatsu" is preferred to the ones of potential.
A Technique to Circumvent V-shaped Deconvolution Error for Time-dependent SRAM Margin Analyses
Somha, Worawit,Yamauchi, Hiroyuki,Yuyu, Ma The Institute of Electronics and Information Engin 2013 IEIE Transactions on Smart Processing & Computing Vol.2 No.4
This paper discusses the issues regarding an abnormal V-shaped error confronting algebraic-based deconvolution process. Deconvolution was applied to an analysis of the effects of the Random Telegraph Noise (RTN) and Random Dopant Fluctuation (RDF) on the overall SRAM margin variations. This paper proposes a technique to suppress the problematic phenomena in the algebraic-based RDF/RTN deconvolution process. The proposed technique can reduce its relative errors by $10^{10}$ to $10^{16}$ fold, which is a sufficient reduction for avoiding the abnormal ringing errors in the RTN deconvolution process. The proposed algebraic-based analyses allowed the following: (1) detection of the truncating point of the TD-MV distributions by the screening test, and (2) predicting the MV-shift-amount by the assisted circuit schemes needed to avoid the out of specs after shipment.