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A 22 GHz cascode CMOS VCO using frequency doubler
Park, Bonghyuk,Lee, Seungsik,Hong, Songcheol,Choi, Sangsung Wiley Subscription Services, Inc., A Wiley Company 2007 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS Vol.49 No.11
<P>This paper presents a fully integrated cascode CMOS LC VCO using frequency doubler for oscillating at 22 GHz band. A symmetrical cascode coupling topology is implemented with negative conductance scheme for increasing the quality factor and output swing. Therefore, this architecture improves the phase noise characteristic in 0.18 μm CMOS technology. In order to oscillate at 22 GHz band the frequency doubler (clipper) is used. The measured phase noise is −102.4 dBc/Hz at the 1 MHz offset frequency. The tuning range of 1.32 GHz is obtained with the control voltage from 0.5 to 1.6 V. The current consumption of the VCO and the frequency doubler has 11.8 mA from 1.8 V supply. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 2870–2873, 2007; Published online in Wiley InterScience (www.interscience.wiley.com).DOI 10.1002/mop.22857</P>
The design of integrated 0.13-μm CMOS receiver for ultra-wideband systems
Park, Bonghyuk,Lee, Kwangchun,Choi, Sangsung,Hong, Songcheol Wiley Subscription Services, Inc., A Wiley Company 2010 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS Vol.52 No.4
<P>A fully integrated 0.13-μm CMOS receiver for ultra-wideband systems is implemented. This receiver enables eight bands of operation covering 3.1–9.0 GHz. The system, based on the Multiband OFDM Alliance standard proposal and consisting of a direct-conversion receiver chain and required noise figure, is discussed. The average conversion gain and input P1dB are 67.3 dB and −25.4 dBm, respectively. The shunt-series feedback low-noise amplifier provides a receiver front-end noise figure of 7.1–9.5 dB over the entire band. The mixer, based on a folded-cascode topology, also implements a four-stage programmable gain amplifier. A fabricated die has been bonded and molded onto PCB for characterization. The receiver chip dissipates 48 mA from 1.2 V power supply. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:841–845, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25083</P>
A High Voltage Swing Dual-Band Bandpass <tex> $\Delta\Sigma$</tex> Modulator for Mobile Base-Station
Bonghyuk Park,Seunghyun Jang,Ostrovskyy, P.,Jaeho Jung IEEE 2013 IEEE microwave and wireless components letters Vol.23 No.4
<P>A fully integrated high voltage swing dual-band continuous-time bandpass delta-sigma modulator (CT BPDSM) with a high voltage swing and fabricated on a 0.25 μm SiGe BiCMOS is presented. The proposed CT BPDSM consists of a two-stage second-order resonator, a high speed comparator, multi-feedback current DACs, and a high voltage swing driver. The band selection is controlled using a capacitor bank, and fine frequency tuning is conducted by a varactor. At 883 and 955 MHz, the implemented BPDSM with a high voltage swing shows a peak SNR of 40.6 and 41.9 dB, and an error vector magnitude (EVM) of 5.48%, 3.48%, respectively. In addition, it has a differential output voltage swing of 1.55 Vp-p with a dc power consumption of 635.3 mW.</P>
Park, Bonghyuk,Lee, Seungsik,Hong, Songcheol,Choi, Sangsung Wiley Subscription Services, Inc., A Wiley Company 2007 MICROWAVE AND OPTICAL TECHNOLOGY LETTERS Vol.49 No.10
<P><B>Abstract</B></P><P>This article presents an effective methodology for designing a CMOS single‐balanced down conversion mixer with LO cancellation for MB‐OFDM UWB direct‐conversion receiver. The most crucial drawback of single‐balanced mixer; LO feedthrough is overcome by employing BPF technique for multi‐channel LO signal. The proposed single‐balanced mixer is implemented with 0.18 μm CMOS technology and it operates from 3 to 5 GHz frequency range. The measurement result shows that LO signal amplitude is less than IF signal, the IIP3 is 1 dBm at 4‐GHz band, and the current consumption is 6 mA. © 2007 Wiley Periodicals, Inc. Microwave Opt Technol Lett 49: 2555–2558, 2007; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.22793</P>
A Low-Noise Amplifier With Tunable Interference Rejection for 3.1- to 10.6-GHz UWB Systems
Bonghyuk Park,Sangsung Choi,Songcheol Hong IEEE 2010 IEEE microwave and wireless components letters Vol.20 No.1
<P>An ultrawideband common-gate low noise amplifier with tunable interference rejection is presented. The proposed LNA embeds a tunable active notch filter to eliminate interferer at 5-GHz WLAN and employs a common-gate input stage and dual-resonant loads for wideband implementation. This LNA has been fabricated in a 0.18-¿m CMOS process. The measured maximum power gain is 13.2 dB and noise figure is 4.5-6.2 dB with bandwidth of 3.1-10.6 GHz. The interferer rejection is 8.2 dB compared to the maximum gain and 7.6 dB noise figure at 5.2 GHz , respectively. The measured input P1dB is -11 dBm at 10.3 GHz. It consumes 12.8 mA from 1.8-V supply voltage.</P>
A 3.1 to 5 GHz CMOS Transceiver for DS-UWB Systems
Bonghyuk Park,Kyungai Lee,홍성철,Sangsung Choi 한국전자통신연구원 2007 ETRI Journal Vol.29 No.4
This paper presents a direct-conversion CMOS transceiver for fully digital DS-UWB systems. The transceiver includes all of the radio building blocks, such as a T/R switch, a low noise amplifier, an I/Q demodulator, a low pass filter, a variable gain amplifier as a receiver, the same receiver blocks as a transmitter including a phaselocked loop (PLL), and a voltage controlled oscillator (VCO). A single-ended-to-differential converter is implemented in the down-conversion mixer and a differential-to-single-ended converter is implemented in the driver amplifier stage. The chip is fabricated on a 9.0 mm2 die using standard 0.18 μm CMOS technology and a 64-pin MicroLead Frame package. Experimental results show the total current consumption is 143 mA including the PLL and VCO. The chip has a 3.5 dB receiver gain flatness at the 660 MHz bandwidth. These results indicate that the architecture and circuits are adaptable to the implementation of a wideband, low-power, and high-speed wireless personal area network.
GaN HEMT MMIC Doherty Power Amplifier With High Gain and High PAE
Park, Yunsik,Lee, Juyeon,Jee, Seunghoon,Kim, Seokhyeon,Kim, Cheol Ho,Park, Bonghyuk,Kim, Bumman IEEE 2015 IEEE microwave and wireless components letters Vol.25 No.3
<P>This paper presents an approach to maximize the gain and power-added efficiency (PAE) of a Doherty power amplifier (PA) using a 0.25 <TEX>$\mu$</TEX>m GaN pHEMT. The conventional carrier PA has an input matching for the <TEX>${R}_{\rm OPT}$</TEX> load and does not deliver the 3 dB higher gain with <TEX>${2R}_{\rm OPT}$</TEX> load due to the mismatch and it degrades gain and PAE of the PA. To solve the problem, the input match of the carrier PA is optimized at the back-off power level with the <TEX>${2R}_{\rm OPT}$</TEX> output load, while the input is mismatched at a high power level. A Doherty PA with the concept is designed and implemented using a GaN pHEMT MMIC process at 1.8 GHz. The measured average output power, power-added efficiency and gain are 35.6 dBm, 56.3%, and 18.9 dB for a 10 MHz LTE signal with a 6.5 dB PAPR.</P>