텅스텐 폴리사이드막의 열산화에서 인 불순물 효과

정회환(Hoi Hwan Chung),정관수(Kwan Soo Chung) 한국진공학회(ASCT) 1995 Applied Science and Convergence Technology Vol.4 No.3

P-doped poly-Si/SiO₂/Si 기판위에 저압 화학 증착법(LPCVD)으로 증착한 텅스텐 실리사이드(WSi_2.7)막을 850℃에서 20분 동안 N₂ 분위기에서 열처리한 후에 건식 분위기에서 열산화하였다. 다결정 실리콘의 인도핑(doping) 레벨에 따른 텅스텐 폴리사이드(WSi_2.5/poly-Si)막의 산화 성장율과 텅스텐 폴리사이드막의 산화 메카니즘에 대하여 연구하였다. 텅스텐 폴리사이드막의 산화 성장율은 다결정 실리콘의 인(P) 도핑 레벨이 증가함에 따라 증가하였다. 텅스텐 폴리사이드막의 산화는 텅스텐 실리사이드층의 과잉(excess) Si가 초기 산화 과정 동안 소모된 후에 다결정 실리콘층의 Si가 소모되었다. 산화막과 산화막을 식각(etching)한 후에 텅스텐 실리사이드막의 표면 거칠기는 다결정 실리콘의 인 농도가 적을수록 평탄하였다. Tungsten silicide (WSi_2.7) films deposited by LPCVD (low pressure chemical vapor deposition) onto a P-doped polysilicon/SiO₂/Si substrate were oxidized in dry O₂ ambients after fumace annealing in N₂ at 850℃ for 20 min. The oxidation rate of the tungsten polycide (WSi_2.5/poly-Si) films as a function of phosphorus doping levels in the polysilicon and the oxidation mechanism of the tungsten polycide film have been studied. The oxidation rate of the tungsten polycide films increases with an increase of the phosphorus concentration in the polysilicon. The silicon from the underlying polysilicon layer begins to be consumed after all the excess silicon in the tungsten silicide layer is consumed first oxidation. The surface roughness of oxides and the tungsten silicide films after oxide etching was found to be very smooth at the low p-doped polysilicon.

W - Polycide 게이트 구조에서 텅스텐 실리사이드 증착 방법에 따른 게이트 산화막의 내압 특성

정회환(Hoi Hwan Chung),정관수(Kwan Soo Chung) 한국진공학회(ASCT) 1995 Applied Science and Convergence Technology Vol.4 No.3

습식 분위기로 성장한 게이트 산화막 위에 다결정 실리콘(poly-Si)과 텅스텐 폴리사이드 (WSi_x/poly-Si) 게이트 전극을 형성하여 제작한 금속-산화물-반도체(metal-oxide-semiconductor : MOS)의 전기적 특성을 순간 절연파괴(time zero dielectric breakdown : TZDB)로 평가하였다. 탱스텐 폴리사이드 게이트 전극에 따른 게이트 산화막의 평균 파괴전계는 다결정 실리콘 전극보다 1.93 MV/cm 정도 낮았다. 텅스텐 폴리사이드 게이트 전극에서 게이트 산화막의 B mode(1~8 MV/㎝) 불량률은 dry O₂ 분위기에서 열처리함으로써 증가하였다. 이것은 열처리함으로써 게이트 산화막에 불소 (fluorine)의 확산에 기인하였다. Dichlorosilane(SiH₂Cl₂) 환원에 의한 텅스텐 폴리사이드 게이트 전극이 silane(SiH₄)에 의한 것보다 B mode 불량률이 감소하였다. 그것은 dichlorosilane 환원에 의한 텅스텐 실리사이드내의 불소 농도가 silane에 의한 것보다 낮기 때문이다. The electrical characteristics of metal-oxide-semiconductor(MOS) fabricated by polysilicon and tungsten polycide(WSi_x/polysilicon) gate electrodes onto gate oxide grown by wet ambients were evaluated by time zero dielectric breakdown(TZDB). The average breakdown field of the gate oxides with tungsten polycide gate electrode was 1.93 MV/㎝ lower than that of the polysilicon gate electrode. The B mode(1~8 MV/㎝) failure of the gate oxides with tungsten polycide gate electrode was decreased by annealing in dry O₂ ambient. This is attributed to fluorine diffusion in the gate oxide by annealing. The B mode failure of the tungsten polycide gate electrode by dichlorosilane(SiH₂Cl₂) reduction was higher than that of the silane(SiH₄) reduction. It is found that the fluorine concentration in the tungsten silicide film by dichlorosilane was lower than that of the silane reduction.

비정질 실리콘을 이용한 다층 유전 박막의 전기적 특성에 관한 연구

정회환(Hoi Hwan Chung),정관수(Kwan Soo Chung) 한국진공학회(ASCT) 1994 Applied Science and Convergence Technology Vol.3 No.1

ANO 구조의 캐패시터 유전체막의 전기적인 특성을 ONO 구조의 캐패시터 유전체막의 경우와 비교하였다. ONO막과 ANO막의 전기적 특성은 고주파(1 ㎒) C-V, 정전압 stress 후 고주파 C-V, I-V, TDDB와 refresh time을 측정하여 평가하였다. ANO막이 ONO막보다 높은 절연파괴전하(Q_(BD))와 축적용량을 가졌고, 긴 refresh time을 가지는 우수한 전기적 특성을 나타냈다. 또한, ONO막과 ANO막과의 누설전류와 flat band 전압변화 (△V_(fb))에서도 거의 차이가 없었다. The electrical characteristics of the capacitor dielectric films of amorphous silicon-nitride-oxide(ANO) structures are compared with the capacitor dielectric films of oxide-nitride-oxide(ONO) structures. The electrical characteristics of ONO and ANO films were evaluated by high frequency(1 ㎒) C-V, high frequency C-V after constant voltage stress, I-V, TDDB, and refresh time measurements. ANO films shows good electrical characteristics such as higher total charge to breakdown(Q_(BD)), storage capacitance and longer refresh time than ONO films. Also, it makes little difference that leakage current and flat band voltage shift(△V_(fb)) of ANO and ONO films.

전극 재료와 산화분위기에 따른 게이트 산화막의 전기적 특성에 관한 연구

정회환(Hoi Hwan Chung),정관수(Kwan Soo Chung) 한국진공학회(ASCT) 1995 Applied Science and Convergence Technology Vol.4 No.1

건식, 습식, 건식/습식 산화분위기로 성장한 게이트 산화막 위에 Al, 인 도핑된 다결정 실리콘, 비정질 실리콘/인 도핑된 다결정 실리콘을 증착하여 제작한 금속-산화물-반도체(metal-oxide-semiconductor:MOS)의 전기적 특성을 순간 절연파괴(TZDB), 정전용량-전압(C-V)과 경시절연파괴(TDDB)로 평가하였다. Al 게이트에서 습식산화막과 건식산화막의 평균 파괴전계는 각각 9.0 MV/㎝, 7.7 MV/㎝이였고, 습식산화막이 건식산화막보다 낮은 유동전하(Q_m)와 계면 고정전하(Q_(ss))을 가졌다. 다결정 실리콘 게이트에서는 습식산화악의 평균 파괴전계가 8.4 MV/㎝ 이였으며, Al 게이트보다 0.6 MV/㎝ 정도 낮았다. 이것은 다결정 실리콘/습식산화막 계면에서 인(phosphorus) 확산으로 다결정 실리콘의 grain 성장과 산화막의 migration에 의한 roughness 증가에 기인한다. 그러나 다결정 실리콘/건식산화막 계면에서 roughness 증가는 없었다. 다결정 실리콘 게이트에서는 건식/습식 산화막이 건식산화막과 습식산화막보다 평균 파괴전계와 절연파괴전하(Q_(BD))가 높았다. 또한 다결정/비정질 실리콘 게이트에서는 습식산화막의 평균 파괴전계가 8.8MV/㎝이였으며, 다결정 실리콘 게이트에서 보다 0.4MV/㎝ 정도 높았다. 다결정/비정질 실리콘 구조는 앞으로 VLSI 적용에 있어서 게이트 전극으로 매우 유용할 것이다. The electrical characteristics of metal-oxide-semiconductor(MOS) fabricated by depositing Al, phosphorus(P)-doped polysilicon and amorphous silicon(a-Si)/P-doped polysilicon(poly-Si) onto gate oxide grown by dry, wet and dry/wet oxidation ambients were evaluated by time zero dielectric breakdown(TZDB), capacitance-voltage(C-V) and time dependent dielectric breakdown(TDDB). The average breakdown field of the wet and the dry oxides with Al gate was 9.0 MV/㎝, 7.7 MV/㎝ repectively. The wet oxides with Al gate have lower Q_m(mobile oxide charge) and Q_ss(fixed oxide charge) than that of the dry oxides. The average breakdown field of the wet oxides with poly-Si gate was 8.4 MV/㎝, 0.6 MV/㎝ lower than those of the Al gate. This is attributed to the increase of roughness due to the grain growth of poly-Si gate and migration of oxide by phosphorus diffusion at the poly-Si/wet oxide interface. But, there was no the increase of roughness at the poly-Si/dry oxide interface. The average breakdown field and the total charge to breakdown (Q_(BD)) of the dry/wet oxides with poly-Si gate have higher than that of the dry, and wet oxides. Also, the average breakdown field of the wet oxides with a-Si/poly-Si gate was 8.8 MV/㎝, 0.4 MV/㎝ higher than that of the poly-Si gate. It is believed that this structure can offer a superior performance for gate electrode in furture YLSI applications.

실리콘 기판과 ITO 가 코팅된 #7059 유리 기판간의 정전 열 접합

주병권,정회환,김영조,한정인,조경익,오명환 ( Byeong Kwon Ju,Hoi Hwan Chung,Young Cho Kim,Jeong In Han,Kyoung Ik Cho,Myung Hwan Oh ) 한국센서학회 1998 센서학회지 Vol.7 No.3

Si and ITO-coated #7059 glass wafers were electrostatically bonded by employing 7740 interlayer. It was inferred that the thermionic electrostatic migration of Na^+ ions in the #7740 interlayer played an important role in the bonding process through SIMS analysis. The temperature and voltage required for reliable electrostatic bonding were in the range of 180∼200℃ and 50∼70V_(dc)(10min), respectively. The low temperature Si-ITO coated glass bonding can be effectively applied to the packaging of field emission devices.

비정질/다결정 실리콘 Gate를 이용한 Gate 산화막 특성 개선

정회환,정관수 慶熙大學校 材料科學技術硏究所 1992 材料科學技術硏究論集 Vol.5 No.-

The polysilicon films were deposited in a LPCVD furnace on oxidized substrates at temperatures above 620℃. The polysilicon gates were doped by a LPCVD furnace with POCl_(3) as the dopant gas. Dopant diffusion through the gate can lead to a degradation of the electrical properties. The interface properties have been characterized SIMS, ASR analysis. We have studied the breakdown properties of MOS fabricatied by depositing polysilicon on very thin(200Å) gate oxides grown by wet oxidation in a conventional furnace. The amorphous/poly silicon gates have higher breakdown field than the polysilicon gates.

Scanning Tunneling Microscope(STM)의 제작

김동식,정회환,정관수 慶熙大學校 材料科學技術硏究所 1993 材料科學技術硏究論集 Vol.6 No.-

In this paper, we have designed and constructed a scanning tunneling microscope(STM) for studying on the atomic scale strucure of semiconductor surfaces We considered next four points. Firstly, we used triple spring damping system for stable measurement. Secondly, we soldered electronic part on PCB board to minimize electronic noise. Thirdly, we made stable power supply part to reduce drift power noise. Fourthly, stainless steel 302 was used for future UHV experiment. In operating the STM, we could eliminate the effect of external vibration by adopting the triple spring damping system. Noise of 60 Hz which was generated by wire connection between electronic and mechanical part, was eliminated by drying the silver paste thoroughly. Tip voltage was biased by 10mV We have obtained clear images of HOPG(high oriented pyrolitic graphite) when tunneling current was 2nA. In conclusion, we have confirmed that our STM have a resolution of atomic scale by investigation of the image of HOPG surface.