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Buried oxide 구조 활용을 통한 1.2 kV SiC MOSFET의 Gate charge 특성 개선 연구
윤효원(Hyowon Yoon),김진훈(Jinhun Kim),김채윤(Chaeyun Kim),박영은(Yeongeun Park),김광재(Gwangjae Kim),김상엽(Sangyeob Kim),신강희(Kanghee Shin),박수민(Sumin Park),석오균(Ogyun Seok) 대한전자공학회 2023 대한전자공학회 학술대회 Vol.2023 No.6
A 1.2 kV SiC MOSFET with buried oxide structure to improve gate charge characteristics was proposed. To verify the performance of 1.2 kV SiC MOSFET with buried oxide, we analyzed electrical characteristics of devices according to width (WBO) and depth of buried oxide (TBO). As a result, the QGD of 1.2 kV SiC MOSFET with optimized buried oxide having WBO of 0.2 μm and TBO of 0.1 μm was reduced by 32.8 % than that of 1.2 kV SiC MOSFET with planar MOS structure.