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센서 재료 , 제조공정 및 기타 : SPICE 를 사용한 표면음파 필터의 시뮬레이션
유상대(Sang Dae Yu) 한국센서학회 2001 센서학회지 Vol.10 No.2
Using transmission-line equivalent circuit based on cross-field model for an interdigital acoustic wave transducer, an efficient simulation technique of SAW filters by SPICE is proposed. Propagation of surface acoustic wave is modeled as transmission line so that frequency-dependent circuit elements are not needed in the equivalent circuit of an interdigital transducer. Because the equivalent circuits for frequency-dependent circuit elements are not derived approximately, and a small number of circuit elements are used in the equivalent circuit for filters, simulation time is much reduced. The utility of the proposed technique is demonstrated through simulation for the characteristics of SAW filters such as insertion loss, input admittance, passband ripple, and harmonic frequency response.
유상대 ( Sang Dae Yu ) 한국센서학회 1997 센서학회지 Vol.6 No.2
Based on a new search strategy using circuit simulation and simulated annealing with local search, a technique for design automation of high-performance operational amplifiers is proposed. For arbitrary circuit topology and performance specifications, through discrete optimization of a cost function with discrete design variables the design of operational amplifiers is performed. A special-purpose circuit simulator and some heuristics are used to reduce the design time. Through the design of a low-power high-speed fully differential CMOS operational amplifier usable in smart sensors and 10-b 25-MS/s pipelined A/D converters, it has been demonstrated that a design tool developed using the proposed technique can be used for designing high-performance operational amplifiers with less design knowledge and less design effort.
10-bit 40 MS/s 저전력 CMOS 파이프라인 A/D 변환기 설계
이세영,유상대 ( Sea Young Lee,Sang Dae Yu ) 한국센서학회 1997 센서학회지 Vol.6 No.2
In this paper, the design of a 10-bit 40-MS/s pipelined A/D converter is implemented to achieve low static power dissipation of 70 mW at the ±2.5 V or +5 V power supply environment for high speed applications. A 1.5 b/stage pipeline architecture in the proposed ADC is used to allow large correction range for comparator offset and perform the fast interstage signal processing. According to necessity of high-performance op amps far design of the ADC, the new op amp with gain boosting based on a typical folded-cascode architecture is designed by using SAPICE that is an automatic design tool of op amps based on circuit simulation. A dynamic comparator with a capacitive reference voltage divider that consumes nearly no static power for this low power ADC was adopted. The ADC implemented using a 1.0 ㎛ n-well CMOS technology exhibits a DNL of ±6 LSB, INL of +1/-0.75 LSB and SNDR of 56.3 dB for 9.97 MHz input while sampling at 40 MHz.
샘플-앤-홀드를 이용한 AMOLED 디스플레이 구동 회로의 설계
최성욱(Sung-Wook Choi),이주상(Ju-Sang Lee),유상대(Sang-Dae Yu) 대한전자공학회 2007 대한전자공학회 학술대회 Vol.2007 No.7
In this paper, the designed 8-bit current steering data driving circuit using Sample-and-Hold consists of bias circuits, shift registers, data and line latches, level shifters, and 8-bit D/A converters, current mode Sample-and-Hold. This data driving circuit can improve image quality, driving speed, and can reduce process error, DNL error, and glitch noise, and circuits area. To reduce current cells, the 8-bit D/A converter was designed 4+4 hybrid type. The transient analysis shows that currents flows a few of uA in data line, and the currents have 256 gray levels of current values. Total circuits are designed for 10 ㎲ speed. Thus the designed 8-bit current steering data driving circuit can be usable in QVGA AMOLED displays. These data driving circuits are designed for 0.35 ㎛ CMOS process at 2.5 V and 5 V supply voltage and simulated with HSPICE.
박석홍,손영찬,유상대 ( Seog Hong Park,Yeong Chan Son,Sang Dae Yu ) 한국센서학회 1996 센서학회지 Vol.5 No.4
This paper presents the optimal design method of SAW filters with arbitrary frequency characteristics. The design program using the unconstrained nonlinear optimization method and FFT algorithm is developed for optimal design of SAW filters with arbitrary frequency characteristics. As a design example, a SAW TV IF filter with asymmetric-amplitude and nonlinear-phase frequency characteristics is designed.
마스크 레이아웃 합성을 위한 벡터화한 변을 사용한 블록 분할 기법
손영찬,주이아,유상대,Son, Yeong-Chan,Ju, Ri-A,Yu, Sang-Dae 대한전자공학회 2001 電子工學會論文誌-SD (Semiconductor and devices) Vol.38 No.12
Due to the high density of integration in current integrated circuit layouts, circuit elements must be designed to minimize the effect of parasitic elements and thereby minimize the factors which can degrade circuit performance. Thus, before making a chip, circuit designers should check whether the extracted netlist is correct, and verify from a simulation whether the circuit performance satisfies the design specifications. In this paper, we propose a new block disassembly technique which can extract the geometric parameters of stacked MOSFETs and the distributed RCs of layout blocks. After applying this to the layout of a folded-cascode CMOS operational amplifier, we verified the connectivity and the effect of the components by simulating the extracted netlist with HSPICE. 오늘날 집적회로의 집적도가 증가되고 있기 때문에 회로 소자는 기생성분의 영향을 최소화하고 회로의 성능을 감소시키는 요인을 최소화하도록 설계되어야 한다. 그래서 칩을 제작하기 전에 레이아웃으로부터 추출한 회로가 정확한가를 검증하고 시뮬레이션으로 추출된 회로가 설계사양을 만족하는지를 확인해야 한다. 본 논문에서는 스택 구조의 MOSFET의 기하학적인 파라미터와 레이아웃 배선 블록의 분산 RC를 추출할 수 있는 새로운 블록 분할 기법을 제안한다. 폴디드 캐스코드 CMOS 연산 증폭기의 레이아웃에 이 기법을 작용하여 회로를 추출하고, Hspice로 시뮬레이션을 수행하여 전기적 연결관계와 이들 소자의 영향을 검증하였다.