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宋洛雲,趙德垠 弘益大學校 科學技術硏究所 2002 科學技術硏究論文集 Vol.13 No.-
In this paper, the encoder is designed using SPIHT(Set Partitioning in Hierarchical Trees) algorithm for efficient image compression. Here, 5 RAM is used and simplified address generator is designed where the comparator using two values is adopted. In the simulation of the suggested architecture, the improved performance is confirmed.
송낙운,임윤환 弘益大學校 科學技術硏究所 2000 科學技術硏究論文集 Vol.11 No.-
In this paper, two-dimensional wavelet encoder with efficient architecture for real-time image processing is designed. The architecture consists of parallel filter, input control unit and address control unit, and threee storage module is used to simplify related control units. Further, boundary data unit is made for perfect image decoding and scheduling method is adopted to control restricted hardware efficiently. The designed encoder is simulated by C and VHDL language, where reasonable capability is confirmed.
宋洛雲,朴世俊 弘益大學校 科學技術硏究所 2004 科學技術硏究論文集 Vol.15 No.-
In this paper the architecture of turbo decoder using HR-SOVA algorithm is proposed. Here, turbo encoder and turbo decoder by RE-SMU block is designed to increase the simplification and speed. The designed architecture is simulated by C++ and VHDL, and normal performance is confirmed.
宋洛雲 弘益大學校 科學技術硏究所 1992 科學技術硏究論文集 Vol.2 No.-
In this work, the VLSI design framework is made by establishing design methodology with respect to the corresponding design levels. To achieve this, the related design CAD softwares, i.e., critical path calculation, schedulingr by simulated annealing, VHDL works, are developed at each design level. The MPC chip is made by the prepared CAD design environment, and presently the data paths such as Booth multiplier, ALU, are designed.
宋洛雲,金將起 단국대학교 1981 論文集 Vol.15 No.-
An exact formula is given for the Goos-Ha¨nchen shift occuring for the TIR(total internal reflection) of light through the thin-film mode converter by the coupled-wave analysis to calculate the coupling coefficient.
송낙운 弘益大學校 科學技術硏究所 1993 科學技術硏究論文集 Vol.3 No.-
본 연구에서는 교육용 VHDL 및 관련 CAD 툴을 사용하여 대표적인 디지탈 시스템, 즉, 마이크로프로세서, 디지탈 필터의 설계를 수행한다. VHDL 모의해석의 경우, 행위/구조 모델링을 사용하여 모의해석하였으며, 주어진 입력에 대하여 정상적으로 동작하였으며, 이를 교육용 CAD 툴에 의해 풀커스텀/세미커스텀 설계방식에 의해 레이아웃을 수행하였을때 유사한 결과를 얻을 수가 있었다. 아울러 관련 문제점 및 향후 연구 방향에 관해 논한다. In this work. typical digital systems designs, e.g., microprocessor unit, digital filter, are implemented using education-purpose VHDL and CAD tools. In VHDL simulation, the simulation results using behavioral/structural modeling are performed normally for given inputs and similar results are obtained when layouts are made by full-custom/semi-custom design methods using educational CAD tools. Further, related problems and future research directions are discussed.
개선된 시뮬레이티드어닐링 기법에 의한 디지탈필터 설계의 고찰
송낙운,윤복식,Song, Nag-Un,Yun, Bok, Sik 한국정보처리학회 1995 정보처리논문지 Vol.2 No.1
본 연구에서는 스케쥴링과 하드웨어 할당에 관련된 상위단계합성에서 최적설계 방법론을 효과적으로 변형된 시뮬레이티드 어닐링 기법을 사용하여 정립한다. 또한 정립된 기법을 디지탈필터(DF : digital filter)의 설계에 적용하여 파이프라인 DF 의 경우 최적설계시에 속도와 하드웨어의 최적의 절충 문제와 어레이 DF에서의 해석 에 관련된 문제점을 검토한다. 이러한 적용사례를 통해 제안된 방법이 보다 빠른 시간 에 향상된 비용함수값을 줄 수 있음이 확인되고 복잡한 디지탈필터 설계에 이용될 수 있음이 입증된다. In this work, the optimized design methodology in high-level synthesis related with scheduling and hardware allocation is developed by simulated annealing technique effectively modified . Applying this method to digital filter design, the optimized tradeoff problem of speed and hardware costs in pipelined digital filter case and array digital filter case are investigated. While, it is confirmed that the suggested method gives the improved cost function value faster and can be used in complicated digital filter design.
송낙운 弘益大學校 科學技術硏究所 1994 科學技術硏究論文集 Vol.5 No.-
In this work, 2D FIR DF is designed and simulated by C. VHDL languages. Designed two-dimensional digital filter mainly consists of one-dimensional digital filter and line memory. Once digital filter coefficients are represented by CSD(Canonical signed Digit) formats, multipliers are realized by hardwired-shifting methods. To speed up the 1D DF block, carry-save adder in each tap and Manchester adder in every 1D DF are adopted. The designed filter is performed up to 30 MHZ and related layouts are now in progress by Berkeley CAD tools.
宋洛雲 弘益大學校 1990 弘大論叢 Vol.22 No.2
In this paper, the feasibility of DSP-related IC chip development is studied with respect to world market and technology. It is found that the DSP-related areas, such as HDTV, ISDN, will lead the world semiconductor market in near future. To step up with this fast R&D in this area, it is belived that the top-down design capability, including the cooperation of system designers and semiconductor designers, is obligatory and urgent. Several devices such as codec chips are recommended for development.