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金如煥 관동대학교 1997 關大論文集 Vol.25 No.2
A circuit model for the field emission devices has been proposed. The model parameters have been extracted from the fabricated silicon tip array and verified by comparing with the results simulated by circuit simulator(SPICE). The maximum operating frequency can be calculated from the capacitance and the transconductance(g) of the array. For an emitter array, the capacitance of 3.45×10 pF/tip and the transconductance is 0.6 μS/tip have been measured under the emission current of 10 μA/tip. From these values, the cut-off frequency can be also predicted to be 28 MHz.
金如煥 관동대학교 1999 關大論文集 Vol.27 No.2
In a plat panel display device. operating frequency of driving circuit is very important since performances of display system are limited by this switching speed. LDMOS is mostly used for high voltage ICs since MOSFET has the faster switching ability of majority carrier devices which do not suffer from the minority carrier charge storage problems inherent to bipolar transistor and the negative thermal coefficient of which impurity concentration should be low to reduce the lateral field caused by high drain voltage is necessary in LDMOS. However. lateral field was mitigated by RESURF. and drift region can be shorten in order to reduce drain on-resistance. A new SOI LDMOS structure with the breakdown voltage over 200V for head mount display was proposed and simulated. It could be fabricated by existing 1.2pm CMOS process.
金如煥 관동대학교 2000 關大論文集 Vol.28 No.2
In an plat panel display devices. operating frequency of driving circuit is very important since performances of display system are limited by this switching speed. LDMOS is mostly used for high voltage ICs since MOSFET has the faster switching ability and the negative thermal coefficient of carrier mobility. Drift region in which impurity concentration should be low to reduce the lateral field caused by high drain voltage is necessary in LDMOS. Lateral field was mitigated by RESURF. then drift region can be shorten reducing the drain on-resistance. A new SOI LDMOS structure with the breakdown voltage over 200V for head mount display was fabricated. It is compatible to the existing 1.2㎛ CMOS process.
金如煥 관동대학교 1996 關大論文集 Vol.24 No.1
An investigation of the DC conductivity dependence on As preamorphization effect in p+ poly -Si film is presented. DC conductivity of preamorphized film increases about 26.% compared to that doped with only boron in spite of the carrier compensation effects. XTEM micrograph shows that the structure of film is changed an uniform columnar layer to the bi-layer consist to two different grain sizes. In bilayer film larger grain size(∼0.2 ㎛) located in upper layer of film was growth by As+ amorphization and subsequent recrystallization. However, the other smaller one (∼0.3 ㎛) located in bottom was not changed because of the out of range effected by As+ amorphization. The average conductivity of the bi-layer film mainly depends on the thickness of recrystallized layer.