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구교욱(Kyo-Woog Koo),이연(Yeon-Lee),구경완(Kyung-Wan Koo) 대한전기학회 2019 전기학회논문지 Vol.68 No.11
In the case of display PECVD, VHF is introduced as the driving frequency. In addition, since the electrode shape has a large area rectangular structure, nonuniformity caused by the standing wave effect and skin effect occurs. In this case, even small changes in the process variables affect the nonuniformity. Against this we propose the electric field control method using guide ring as a part of reduction effect and fine tuning. Using the guide ring, the electrical influence and the optimization method were confirmed by the response surface Methodology and Taguchi experiment. It is considered that fine tuning is possible by utilizing the electrical properties of each factor.
대면적 초고주파 용량결합 플라즈마 전극의 전기장 균일도 개선
구교욱(Kyo-Woog Koo),김일중(Il-Jung Kim),구경완(Kyung-Wan Koo) 대한전기학회 2020 전기학회논문지 Vol.69 No.1
Large area PECVD processes have been evolved from HF to VHF technology. The larger the substrate and the higher the frequency, the stronger the standing wave is created at the center of the electrode. In this paper, a seven steps of design process were proposed to improve the standing waves by the shape deformation of electrode concave structure. Sheath thickness of 2 mm and cutting depth of 3.4 mm were simulated under the conditions of circular electrode of 1.1 m diameters, excitation frequency of 40.68MHz and gap of electrode 15mm at 4Torr. The non-uniformity was improved from 9.9%. to 1.1% adapting the processes. The same method was applied to the rectangular electrode to improve the electric field uniformity by cutting the upper electrode by making a mock up in proportion to the processing depth in the direction of the center axis using electric field analysis.
안영기,최중봉,구교욱,조중근,김태성,Ahn, Young-Ki,Choi, Jung-Bong,Koo, Kyo-Woog,Cho, Jung-Keun,Kim, Tae-Sung 한국반도체디스플레이기술학회 2009 반도체디스플레이기술학회지 Vol.8 No.1
Typically, single-wafer wet etching is done by dispensing chemical onto the front and back side of spin wafer. The wafer is fixed by a number of chuck pins, which obstruct the chemical flow and would result in the incomplete removal of the remaining film, which can become a source of contamination in the next process. In this paper, we introduce a novel design of wafer chuck, in which chuck pins are groupped into two and each group of pins fixes the substrate alternatively. Two groups of chuck pins fix the high-speed spin substrate with non contact method using a magnetic material. The actual process has been executed to observe the effectiveness of this new wafer chuck. It was found that the new wafer chuck performed better than the conventional wafer chuck for removing the remaining film from the bevel and edge side of substrate.
안영기,김현종,구교욱,조중근,Ahn, Young-Ki,Kim, Hyun-Jong,Koo, Kyo-Woog,Cho, Jung-Keun 한국반도체디스플레이기술학회 2006 반도체디스플레이기술학회지 Vol.5 No.2
Various methods of making thin film is being used in semiconductor manufacturing process. The most common method in this field includes CVD(Chemical Vapor Deposition) and PVD(Physical Vapor Deposition). Thin film is deposited on both the backside and the frontside of wafers. The thin film deposited on the backside has poor thickness profile, and can contaminate wafers in the following processes. If wafers with the thin film remaining on the backside are immersed in batch type process tank, the thin film fall apart from the backside and contaminate the nearest wafer. Thus, it is necessary to etch the backside of the wafer selectively without etching the frontside, and chemical injection nozzle positioned under the wafer can perform the backside etching. In this study, the backside chemical injection nozzle with optimized chemical injection profile is built for single wafer tool. The evaluation of this nozzle, performed on $Si_3N_4$ layer deposited on the backside of the wafer, shows the etching rate uniformity of less than 5% at the etching rate of more than $1000{\AA}$.
김기준(Ki-Jun Kim),구교욱(Kyo-Woog Koo),임효재(Hyo-Jae Lim),이혁(Hyouk Lee) 대한기계학회 2010 대한기계학회 춘추학술대회 Vol.2010 No.11
e-MMC has made the memory of 32GB using 8-multilayer of 4GB NAND-flash memory. Also it has simplified the chip applying SIP technique. Operating temperature as increase of exothermic temperature along the multi-layer of NAND-flash has highly influenced on life of e-MMC. Therefore it is important that geometry of 8-Multilayered structure has change and design in optimum exothermic condition. In this study, geometry of 8-Multilayered structure is compared the temperature distribution of three different geometries along the numerical analysis. As a result, multi-layer of stair type is more efficient because multi-layer of stair type is about 10degrees lower than vertical multi-layer.
안영기,김현종,성보람찬,구교욱,조중근,Ahn, Young-Ki,Kim, Hyun-Jong,Sung, Bo-Ram-Chan,Koo, Kyo-Woog,Cho, Jung-Keun 한국반도체디스플레이기술학회 2006 반도체디스플레이기술학회지 Vol.5 No.2
Wet etching process in recent semiconductor manufacturing is devided into batch and single wafer type. Batch type wet etching process provides more throughput with poor etching uniformity compared to single wafer type process. Single wafer process achieves better etching uniformity by boom-swing injected chemical on rotating wafer. In this study, etching characteristics of $SiO_2$ layer at room and elevated temperature is evaluated and compared. The difference in etching rate and uniformity of each condition is identified, and the temperature profile of injected chemical is theoretically calculated and compared to that of experimental result. Better etching uniformity is observed with single wafer tool with boom-swing injection compared to single wafer process without boom-swing or batch type tool.
김기준(Ki-Jun Kim),구교욱(Kyo-Woog Koo),임효재(Hyo-Jae Lim),이혁(Hyouk Lee) 한국전산유체공학회 2011 한국전산유체공학회 학술대회논문집 Vol.2011 No.5
The low electric power and high efficiency chips are required because of the appearance of smart phones. Also, high-capacity memory chips are needed. e-MMC(embedded Multi-Media Card) for this is defined by JEDEC(Joint Electron Device Engineering Council). The e-MMC memory for research and development is a memory mulit-chip module of 64GB using 16-multilayers of 4GB NAND-flash momory. And it has simplified the chip by using SIP technique. But mulit-chip module generates high heat by higher integration. According to the result of study, whenever semiconductor chip is about 10℃ higher than the design temperature it makes the life of the chip shorten more than 50%. Therefore, it is required that we solve the problem of heating value and make the efficiency of e-MMC improved. In this study, geometry of 16-multilayered structure is compared the temperature distribution of four different geometries along the numerical analysis. As a result, it is can finned that a multilayer structure of stair type is more efficient than a multilayer structure of vertical type because a multi-layer structure of stair type is about 9℃ lower than a multilayer structure of vertical type.